State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Klimowicz, Adam; Salauyou, V.

doi:10.3390/app12168134

Cited by 3 publications

(7 citation statements)

References 41 publications

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“…The problems of optimizing the characteristics of FSM circuits are discussed in many works, such as, for example, [30][31][32][33][34][35]. An analysis of these and many other works allowed us to draw the following conclusion.…”

Section: Related Workmentioning

confidence: 99%

“…The table of the CM is used to derive SBF (24). In the discussed case, SBF (33) represents the circuit of CPO1 and SBF (34) represents the block CM:…”

Section: Cs Pc(cs) St Fc(st)mentioning

confidence: 99%

“…The elements LUT15-LUT19 implement SBF (33). The elements LUT20-LUT22 implement SBF (34). This means that there are 5 LUTs in the circuit of CPO1 and 3 LUTs in the circuit of the CM.…”

Section: Slut1mentioning

confidence: 99%

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Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible.

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Section: Related Workmentioning

confidence: 99%

“…The table of the CM is used to derive SBF (24). In the discussed case, SBF (33) represents the circuit of CPO1 and SBF (34) represents the block CM:…”

Section: Cs Pc(cs) St Fc(st)mentioning

confidence: 99%

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Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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“…This technique aims to train a software model (called "agent") to give it a certain functionality. This functionality lies in generating desired logical outputs based on either its state or its state and its inputs (it can operate either as a Moore machine or as a Mealy machine [27]).…”

Section: Theoretical Backgroundmentioning

confidence: 99%

Reinforcement Learning Made Affordable for Hardware Verification Engineers

Dinu

Ogrutan

2022

Micromachines

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Constrained random stimulus generation is no longer sufficient to fully simulate the functionality of a digital design. The increasing complexity of today’s hardware devices must be supported by powerful development and simulation environments, powerful computational mechanisms, and appropriate software to exploit them. Reinforcement learning, a powerful technique belonging to the field of artificial intelligence, provides the means to efficiently exploit computational resources to find even the least obvious correlations between configuration parameters, stimuli applied to digital design inputs, and their functional states. This paper, in which a novel software system is used to simplify the analysis of simulation outputs and the generation of input stimuli through reinforcement learning methods, provides important details about the setup of the proposed method to automate the verification process. By understanding how to properly configure a reinforcement algorithm to fit the specifics of a digital design, verification engineers can more quickly adopt this automated and efficient stimulus generation method (compared with classical verification) to bring the digital design to a desired functional state. The results obtained are most promising, with even 52 times fewer steps needed to reach a target state using reinforcement learning than when constrained random stimulus generation was used.

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“…One of these methods is a method of twofold state assignment (TSA) leading to three-level FSM circuits [12]. The TSA is aimed at Mealy FSMs implemented with field-programmable gate arrays (FPGAs) [13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs

2022

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A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes. The second core uses extended state codes. Such an approach allows reducing the number of LUTs in the block of state codes’ transformation. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each partial function for any core is represented by a single-LUT circuit. A formal method is proposed for redistribution of states between these cores. An example of synthesis is shown to explain peculiarities of the proposed method. An example of state redistribution is given. The results of experiments conducted with standard benchmarks show that the double-core approach produces LUT-based FSM circuits with better area-temporal characteristics than they are for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and twofold state assignment). Both the LUT counts and maximum operating frequencies are improved. The gain in LUT counts varies from 5.74% to 36.92%, and the gain in frequency varies from 5.42% to 12.4%. These improvements are connected with a very small growth of the power consumption (less than 1%). The advantages of the proposed approach increase as the number of FSM inputs and states increases.

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State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Cited by 3 publications

References 41 publications

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

Reinforcement Learning Made Affordable for Hardware Verification Engineers

Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs

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