Minimization of average execution time based on speculative FPGA configuration prefetch

Lifa, Adrian; Eles, Petru; Peng, Zebo

doi:10.1109/reconfig.2012.6416761

Cited by 4 publications

(21 citation statements)

References 22 publications

(60 reference statements)

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“…After its execution we want to issue a prefetch for a new module. Let us see how a static prefetch approach works, like [17] or [10]. Since it considers profiling information, regardless of the application's phase, it will issue the prefetch based on the average branch probabilities.…”

Section: Problem Formulationmentioning

confidence: 99%

“…For each application we have evaluated different prefetch techniques using an in-house Monte Carlo simulator (described in [10]) that considers the architectural assumptions described in Sec. II-A.…”

Section: Experimental Evaluationmentioning

confidence: 99%

“…We were interested to see how our approach compares to the current state-of-art, both in static [10] and dynamic prefetching [9], [6]. Thus, we simulated each application using the prefetch queues generated by our approach and those generated by [10], [9] and [6].…”

Section: A Performance Improvementmentioning

confidence: 99%

“…Thus, we simulated each application using the prefetch queues generated by our approach and those generated by [10], [9] and [6]. The parameters for our predictor were chosen, depending on the application size, from the following ranges: α = [0.4, 0.6], q = [2,8], h ∈ [4,16], N ∈ [16,32], M ∈ [8,32].…”

Section: A Performance Improvementmentioning

confidence: 99%

“…Many static algorithms for prefetching were proposed: [9], [12], [17], [10]. All share one limitation: in case of nonstationary behavior, they are unable to adapt, since the prefetch schedule is fixed based on average profiling information.…”

Section: Introduction and Related Workmentioning

confidence: 99%

See 4 more Smart Citations

Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

Lifa

Eles

Peng

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Modern systems demand high performance, as well as high degrees of flexibility and adaptability. Many current applications exhibit a dynamic and nonstationary behavior, having certain characteristics in one phase of their execution, that will change as the applications enter new phases, in a manner unpredictable at design-time. In order to meet the performance requirements of such systems, it is important to have on-line optimization algorithms, coupled with adaptive hardware platforms, that together can adjust to the run-time conditions. We propose an optimization technique that minimizes the expected execution time of an application by dynamically scheduling hardware prefetches. We use a piecewise linear predictor in order to capture correlations and predict the hardware modules to be reached. Experiments show that the proposed algorithm outperforms the previous state-of-art in reducing the expected execution time by up to 27% on average.

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Section: Problem Formulationmentioning

confidence: 99%

Section: Experimental Evaluationmentioning

confidence: 99%

Section: A Performance Improvementmentioning

confidence: 99%

Section: A Performance Improvementmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

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Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

Lifa

Eles

Peng

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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A dynamically reconfigurable multi-functional PLL for SRAM-based FPGA in 65nm CMOS technology

Yang¹,

Chen²,

Li³

et al. 2018

AIP Conference Proceedings

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Abstract. Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. PLL with dynamic reconfiguration capability is always welcomed in FPGA design as it is able to decrease power consumption and simultaneously improve flexibility. In this paper, a multi-functional PLL with dynamic reconfiguration capability for 65nm SRAM-based FPGA is proposed. Firstly, configurable charge pump and loop filter are utilized to optimize the loop bandwidth. Secondly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Thirdly, three configurable dividers are presented for flexible frequency synthesis. Lastly, a configuration block with dynamic reconfiguration function is proposed. Simulation results demonstrate that the proposed multi-functional PLL can output clocks with configurable division ratio, phase shift and duty cycle. The PLL can also be dynamically reconfigured without affecting other parts' running or halting the FPGA device.

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A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Lifa

Eles

Peng

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Many modern applications exhibit a dynamic and non-stationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable FPGA architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx's commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive API, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the SUSAN image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-theart prefetching algorithms, with only a minor energy overhead.Index Terms-FPGA, partial reconfiguration, dynamic configuration prefetching, self-reconfiguring and adaptive platform.

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Minimization of average execution time based on speculative FPGA configuration prefetch

Cited by 4 publications

References 22 publications

Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

A dynamically reconfigurable multi-functional PLL for SRAM-based FPGA in 65nm CMOS technology

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

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