A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Abstract

Many modern applications exhibit a dynamic and non-stationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable FPGA architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx's commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive API, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the SUSAN image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-theart prefetching algorithms, with only a minor energy overhead.Index Terms-FPGA, partial reconfiguration, dynamic configuration prefetching, self-reconfiguring and adaptive platform.

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

“…In Chapter 3 we start by introducing a reconfigurable framework for performance enhancement using partial dynamic reconfiguration of FPGAs [LEP15a]. We propose a hardware implementation based on commercial tools, together with a comprehensive API that enables designers to integrate their applications into our framework with minimal effort.…”

“…"A Reconfigurable Framework for Performance Enhancement with Dynamic FPGA Configuration Prefetching." Accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Journal, 2015 [LEP15a].…”