Dynamic Configuration Prefetching Based on Piecewise Linear Prediction

Nguyễn

Proceedings of the 52nd Annual Design Automation Conference

2015

Coarse-Grained Reconfigurable Architectures (CGRAs), often used as coprocessors for DSP and multimedia kernels, can deliver highly energy-efficient execution for compute-intensive kernels. Simultaneously, stream applications, which consist of many actors and channels connecting them, can provide natural representations for DSP applications, and therefore be a good match for CGRAs. We present our results of mapping DSP applications written in StreamIt language to CGRAs, along with our mapping flow. One important challenge in mapping is how to manage the multitude of kernels in the application for the limited local memory of a CGRA, for which we present a novel integer linear programming-based solution. Our evaluation results demonstrate that our software and hardware optimizations can help generate highly efficient mapping of stream applications to CGRAs, enabling far more energy-efficient executions (7× worse to 50× better) compared to using state-of-the-art GP-GPUs.

Section: Related Workmentioning

confidence: 99%

Optimizing stream program performance on CGRA-based systems

Nguyễn

Proceedings of the 52nd Annual Design Automation Conference

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

“…In [18], a new dynamic optimization approach for configuration prefetching is proposed and evaluated. An on-line piecewise linear predictor is used to capture branch correlations and estimate the likelihood to reach different hardware modules from a prediction point.…”

Section: B Fpga Configuration Prefetchingmentioning

confidence: 99%

“…Dynamic prefetching techniques (e.g. [11], [16], [18]) are suitable for applications with non-stationary behavior, since they provide maximum flexibility and adaptability. On the other hand, the optimization algorithms used for prefetching need to be lightweight and capable to learn on-line what are the best prefetches to apply, given the current run-time conditions.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Lifa

Eles

Peng

2016

Self Cite

Many modern applications exhibit a dynamic and non-stationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable FPGA architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx's commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive API, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the SUSAN image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-theart prefetching algorithms, with only a minor energy overhead.Index Terms-FPGA, partial reconfiguration, dynamic configuration prefetching, self-reconfiguring and adaptive platform.

“…The second approach targets applications that exhibit a dynamic and non-stationary phase behavior. The optimization technique dynamically schedules prefetches at run-time based on a piecewise linear predictor [LEP13]. Our methods achieve high degrees of adaptability and answer the performance requirements of cost-constrained systems.…”

Section: Summary Of Contributionsmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...