Minimising Dynamic Power Consumption in On-Chip Networks

Abstract

Abstract-The provision of a general-purpose on-chip communication network is becoming increasingly important in the design of complex SoCs and chip-multiprocessors. In this paper we explore how the power consumed by such on-chip networks may be reduced through the application of clock and signal gating optimisations. We describe how the effectiveness of such optimisations may be maximised and demonstrate that very large reductions in power requirements are possible. A detailed analysis of where power is consumed in an optimised on-chip network is then provided. Results are obtained from fully place and routed standard-cell designs implemented in a 90nm technology. Our 64-bit on-chip network has a maximum operating frequency of 800MHz, in the best-case the combined latency for traversing a network router and link is a single clock cycle.

The power of communication: Energy-efficient NOCS for FPGAS

“…For example, 100% means that we attempt to inject data on all router ports on each cycle, but the x-axis shows that only 28% of the cycles carry new data into the router. At zero data injection the router standby power, because of the clock toggling, is 13% of the power at maximum data injection, suggesting that clock gating the routers is a useful power optimization [9]. Importantly, router parameters also affect the data injection rate at each port.…”

“…However, there is an extensive body of work discussing the power consumption of NoCs for multiprocessors. Some papers discuss the power breakdown of NoCs by router components and links, and investigate how power varies with different data injection rates in an NoC [8][9][10]. Other work focuses on complete systems and reports the power budgeted for communication using an NoC [11,12].…”

QNoC asynchronous router

“…In addition, clock gating is required for clock power reduction in synchronous implementations [47] [48]. An asynchronous NoC helps eliminate en-route resynchronizations and complex clock distribution.…”

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

“…Besides, clock network also consumes a great deal of chip dynamic power because 2 Journal of Electrical and Computer Engineering the clock is fed to most of sequential circuit blocks on chip, and the clock must switch periodically. As a well-known low-power technique, clock-gating is utilized to reduce chip dynamic power [6] and has been implemented in recent NoC designs [1,7,8]. The Intel Teraflop chip [1] uses the multilevel clock-gating policy and the sleep transistor circuits to reduce both dynamic and leakage power, and it is controlled at fullchip, tile-slice, and individual tile levels based on workloads.…”

“…The Intel Teraflop chip [1] uses the multilevel clock-gating policy and the sleep transistor circuits to reduce both dynamic and leakage power, and it is controlled at fullchip, tile-slice, and individual tile levels based on workloads. In another recent clock-gating design, Mullins [7] applies clock-gating to the on-chip routers at two levels: local clockgating and router level clock-gating.…”