Minimal length diagnostic tests for analog circuits using test history

Gomes, Alfred; Chatterjee, Abhijit

doi:10.1145/307418.307488

Cited by 9 publications

(3 citation statements)

References 12 publications

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“…In transient testing (Gomes and Chatterjee, 1999;Variyam et al, 1999;Burdiek, 2001), the circuit under test (CUT) is excited with a transient test stimulus and the circuit response is sampled at specified time points for fault detection. In this paper a new test signal generation method based on control theory techniques like Pontryagin's maximum principle is presented.…”

Section: Introductionmentioning

confidence: 99%

Test signal generation for analog circuits

Burdiek

Mathis

2003

Adv. Radio Sci.

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Abstract. In this paper a new test signal generation approach for general analog circuits based on the variational calculus and modern control theory methods is presented. The computed transient test signals also called test stimuli are optimal with respect to the detection of a given fault set by means of a predefined merit functional representing a fault detection criterion. The test signal generation problem of finding optimal test stimuli detecting all faults form the fault set is formulated as an optimal control problem. The solution of the optimal control problem representing the test stimuli is computed using an optimization procedure. The optimization procedure is based on the necessary conditions for optimality like the maximum principle of Pontryagin and adjoint circuit equations.

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Section: Introductionmentioning

confidence: 99%

Test signal generation for analog circuits

Burdiek

Mathis

2003

Adv. Radio Sci.

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“…AC tests [8,9] are based on multi-tone periodic stimuli, and are typically used to test a class of circuits whose specifications are strongly related to frequency domain behavior of the circuit. Transient tests [10,5,11,12] are superset of AC and DC tests, hence offering higher fault and yield coverage(see [13] for defns) and greater flexibility in applying complex test sequences. Comprehensive fault models are a key factor, which control the complexity of test generation and the resulting fault coverage.…”

Section: Overview Of Analog Test Generationmentioning

confidence: 99%

Robust optimization based backtrace method for analog circuits

Gomes

Chatterjee

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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In this paper, we propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem(BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the convergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.

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“…In addition, a novel methodology for post-processing called measurement synthesis is presented. In [13], Gomes and Chatterjee present a test generation method with response encoding using test history. However, this is simulation intensive, as each of the faults considered needs to be simulated individually to obtain the optimal test stimulus.…”

Section: Introductionmentioning

confidence: 99%

Constrained specification-based test stimulus generation for analog circuits using nonlinear performance prediction models

Bhattacharya

Chatterjee

Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002

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1 The problem of signature-based testing of analog circuits has received a lot of attention in the recent past. In signature-test, a carefully optimized stimulus is applied to the CUT and its specifications are predicted from the test response. This results in test time reduction by 10X-50X. In this paper, a new test generation approach is presented for optimizing a test stimulus that increases the accuracy of specification prediction from the test response. Nonlinear models are used to map the test response to the circuit's specifications. They are accurate in the regions of the measurement space where the circuit's specifications are the most sensitive to process perturbations and maximum information about the CUT's specifications is contained in the observed test response. The test stimulus can be constrained to lie within a specified bandwidth or a specified voltage or current range. This ability is further used to generate wafer-probe and assembled-package tests.

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Minimal length diagnostic tests for analog circuits using test history

Cited by 9 publications

References 12 publications

Test signal generation for analog circuits

Test signal generation for analog circuits

Robust optimization based backtrace method for analog circuits

Constrained specification-based test stimulus generation for analog circuits using nonlinear performance prediction models

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