This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and backend signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and suppression of jitter-induced sampling noise. By switching the sampling rate of a digitizer, the analog frequency value of the sampled signal can be recovered. The proposed signal reconstruction uses incoherent sub-sampling to reduce hardware complexity. The results of simulation and hardware experiments indicate that the proposed signal reconstruction algorithms are able to reconstruct multi-tone high-speed periodic signals in the discrete time domain. The new signal acquisition technique simplifies signal acquisition hardware for testing and characterization of high-speed analog and digital signals.

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1 : In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (∆Σ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ∆Σ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent oversampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodolgy.

In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated to sequentially synthesize the test stimulus for the entire duration of test. We use a novel measurement procedure to resolve ambiguities in the present measurement sample by using class association information from the previous samples. This sequential formulation of test generation problem enables fault dropping and greatly reduces simulation and optimization effort. Additionally, this method is immune to noise and tests can be easily calibrated for use in hardware testers.

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