MIMO Networks With One-Bit ADCs: Receiver Design and Communication Strategies

Khalili, Abbas; Shirani, Farhad; Erkip, Elza; Eldar, Yonina C.

doi:10.1109/tcomm.2021.3133430

Cited by 17 publications

(21 citation statements)

References 43 publications

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“…• Scenario II: Linear Analog Processing [14], [24], [25]: F II a consists of linear functions f a (Y) = VY, V ∈ R n q ×n r . It was shown that linear analog processing prior to the ADC module increases the high SNR capacity, and the gains are further augmented with the use of analog delay elements.…”

Section: System Modelmentioning

confidence: 99%

“…The proof follows by similar arguments as Theorem 3 of [24] along with proof of Theorem 1 and is omitted for brevity.…”

Section: A Scenario Iii: Polynomials With Arbitrary Degreementioning

confidence: 99%

“…Proof Outline. Following the arguments in Theorem 1 in [24], the maximum number of messages which can be transmitted reliably at high SNR is equal to the maximum number of distinct quantization regions which can be produced in R Rank(h) using the analog processing and ADC operation (as long as it is not greater than 2 n q ). We argue that this number is greater than or equal to the Vapnik-Chervonenkis Dimension (VCdim) of F IV .…”

Section: B Scenario Iv: Polynomials With Bounded Degreementioning

confidence: 99%

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MIMO Systems with One-bit ADCs: Capacity Gains using Nonlinear Analog Operations

Shirani¹,

Aghasi²

2022

Preprint

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Analog to Digital Converters (ADCs) are a major contributor to the energy consumption on the receiver side of millimeter-wave multiple-input multiple-output (MIMO) systems with large antenna arrays. Consequently, there has been significant interest in using low-resolution ADCs along with hybrid beam-forming at MIMO receivers for energy efficiency. However, decreasing the ADC resolution results in performance loss -in terms of achievable rates -due to increased quantization error. In this work, we study the application of practically implementable nonlinear analog operations, prior to sampling and quantization at the ADCs, as a way to mitigate the aforementioned rate-loss. A receiver architecture consisting of linear analog combiners, implementable nonlinear analog operators, and one-bit threshold ADCs is designed.The fundamental information theoretic performance limits of the resulting communication system, in terms of achievable rates, are investigated under various assumptions on the set of implementable nonlinear analog functions. In order to justify the feasibility of the nonlinear operations in the proposed receiver architecture, an analog circuit is introduced, and circuit simulations exhibiting the generation of the desired nonlinear analog operations are provided.

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Section: System Modelmentioning

confidence: 99%

“…The proof follows by similar arguments as Theorem 3 of [24] along with proof of Theorem 1 and is omitted for brevity.…”

Section: A Scenario Iii: Polynomials With Arbitrary Degreementioning

confidence: 99%

Section: B Scenario Iv: Polynomials With Bounded Degreementioning

confidence: 99%

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MIMO Systems with One-bit ADCs: Capacity Gains using Nonlinear Analog Operations

Shirani¹,

Aghasi²

2022

Preprint

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“…• Using the data processing inequality (DPI), we establish a new capacity upper bound in the finite SNR regime for the hybrid one-shot receiver with zero threshold ADCs. More precisely, by showing that the amplitude information is discarded in the zero threshold ADC case, we obtain an upper bound that is tighter than the truncated Shannon capacity (TSC) used in [36].…”

mentioning

confidence: 95%

“…These architectures include the mixed-ADC receivers [29], hybrid analog/digital receivers [30]- [33], and machine learning (ML)-based receivers [34], [35]. In [36], the authors suggest two new receiver designs, namely the hybrid blockwise receiver and adaptive threshold receiver, that perform analog spatial and temporal processing prior to 1-bit quantization. The idea of using analog linear combiners prior to 1-bit quantization, called the hybrid one-shot receiver, was initially proposed in [37] as a means to compare performance of different MIMO systems under various output quantization constraints.…”

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confidence: 99%

Capacity Bounds for One-Bit MIMO Gaussian Channels with Analog Combining

Bernardo¹,

Zhu²,

Eldar³

et al. 2022

Preprint

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The use of 1-bit analog-to-digital converters (ADCs) is seen as a promising approach to significantly reduce the power consumption and hardware cost of multiple-input multiple-output (MIMO) receivers.However, the nonlinear distortion due to 1-bit quantization fundamentally changes the optimal communication strategy and also imposes a capacity penalty to the system. In this paper, the capacity of a Gaussian MIMO channel in which the antenna outputs are processed by an analog linear combiner and then quantized by a set of zero threshold ADCs is studied. A new capacity upper bound for the zero threshold case is established that is tighter than the bounds available in the literature. In addition, we propose an achievability scheme which configures the analog combiner to create parallel Gaussian channels with phase quantization at the output. Under this class of analog combiners, an algorithm is presented that identifies the analog combiner and input distribution that maximize the achievable rate. Numerical results are provided showing that the rate of the achievability scheme is tight in the low signal-to-noise ratio (SNR) regime. Finally, a new 1-bit MIMO receiver architecture which employs analog temporal and spatial processing is proposed.The proposed receiver attains the capacity in the high SNR regime.

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Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

Sharroush,

Abdalla

2024

Integration

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MIMO Networks With One-Bit ADCs: Receiver Design and Communication Strategies

Cited by 17 publications

References 43 publications

MIMO Systems with One-bit ADCs: Capacity Gains using Nonlinear Analog Operations

MIMO Systems with One-bit ADCs: Capacity Gains using Nonlinear Analog Operations

Capacity Bounds for One-Bit MIMO Gaussian Channels with Analog Combining

Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

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