Microprocessor Testing: Functional Meets Structural Test

Touati, A.; Bosio, Alberto; Girard, Patrick; Virazel, Arnaud; Bernardi, P.; Reorda, M. Sonza

doi:10.1142/s0218126617400072

Cited by 5 publications

(3 citation statements)

References 2 publications

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“…Others focused on a comparison between the Fault Coverage achievable with scan with respect to the one of SBST, taking also into account the untestable delay faults [9]. Some works also tried to provide techniques allowing to automate the generation of such programs [3][7], possibly resorting to a hybridization between DfT and SBST [25]. Finally, some recent works focused on new techniques to speed up the assessment of the quality of the developed test programs [26].…”

Section: Related Workmentioning

confidence: 99%

Software-Based Self-Test for Delay Faults

Grosso¹,

Reorda²,

Rinaudo³

2020

IFIP Advances in Information and Communication Technology

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Digital integrated circuits require thorough testing in order to guarantee product quality. This is usually achieved with the use of scan chains and automatically generated test patterns. However, functional approaches are often used to complement test suites. Software-Based Self-Test (SBST) can be used to increase defect coverage in microcontrollers, to replace part of the scan pattern set to reduce tester requirements, or to complement the defect coverage achieved by structural techniques when advanced semiconductor technologies introduce new defect types. Delay testing has become common practice with VLSI integration, and with the latest technologies, targeting small delay defects (SDDs) has become necessary. This chapter deals with SBST for delay faults and describes a case of study based on a peripheral module integrated in a System on Chip (SoC). A method to develop an effective functional test is first described. A comparative analysis of the delay faults detected by scan and SBST is then presented, with some discussion about the obtained results.

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Section: Related Workmentioning

confidence: 99%

Software-Based Self-Test for Delay Faults

Grosso¹,

Reorda²,

Rinaudo³

2020

IFIP Advances in Information and Communication Technology

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“…In conventional SBST methods, the whole test program is required to be executed at once [35][36][37]. Execution of a test program assuming that the test program is stored in the cache memory takes a processing core several thousand cycles.…”

Section: Test Snippet and Segmented Test Applicationmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

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“…Software-Based Self-Testing (SBST) is an emerging new paradigm in the testing domain, which relies on the exploitation of existing available resources resident in the system. The SBST approach is based on software programs that are designed to test the functionality of the processor, and they target either general-purpose microprocessors [7] [8][9] [10] [11] [12] [13] [14], or embedded microprocessors and microcontrollers [15] [16] [17] [18] [19]. Specialized test routines (software programs) are executed just like normal programs by the CPU cores under test.…”

Section: Introductionmentioning

confidence: 99%

Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

2018

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As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, firstly we investigate the relation between system test latency and test-time overhead in multi-/many-core systems with shared Last-Level Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. Secondly, we propose a new methodology aiming to reduce the extra overhead related to testing that is incurred as the system scales up (i.e., the number of on-chip cores increases). The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system test session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relationship between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for the actual workloads. Under given system test latency constraints, which dictate the recovery time in the event

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Microprocessor Testing: Functional Meets Structural Test

Cited by 5 publications

References 2 publications

Software-Based Self-Test for Delay Faults

Software-Based Self-Test for Delay Faults

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

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