Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

Abstract

As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, firstly we investigate the relation between system test latency and test-time overhead in multi-/many-core systems with shared Last-Level Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. Secondly, we propose a new methodology aiming to reduce the extra overhead related to testing that is incurred as the system scales up (i.e., the number of on-chip cores increases). The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system test session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relationship between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for the actual workloads. Under given system test latency constraints, which dictate the recovery time in the event

On-Chip Dynamic Resource Management

“…The integration of the SBST approach within the dynamic resource management framework is obtained by enhancing the scheduling algorithm in order to issue self-test routines periodically based on a specific policy. As discussed by Skitsas et al (2018), there are two possible scheduling approaches:…”

“…• run SBST routines on the various cores independently based on a given period (e.g. Skitsas et al (2018)) or selectively based on a priority rule (e.g. Skitsas et al (2016); Haghbayan et al (2016b)).…”

“…Being memory intensive programs, SBST routines executed by some core can be subsequently reused from some other units sharing some cache level so that cache hit percentage is maximized and consequently performance overhead is limited. Finally, other two approaches proposed by Skitsas et al (2018); Kaliorakis et al (2014) perform periodic test scheduling by considering the memory hierarchy in a similar way as Skitsas et al (2016) considering multi-core and many-core architectures, respectively, with the aim at minimizing the overall test time thus increasing the service time.…”

Trends in On-chip Dynamic Resource Management

“…both transient and permanent faults, while other strategies (e.g. [88], [89]) schedule at runtime software-based self testing routines to identify permanent damages.…”

Fragmented software‐based self‐test technique for online intermittent fault detection in processors

“…If not, some of them might go undetected. The traditional permanent and temporary fault detection methods [6–11] have proposed intrusive techniques which embed extra hardware circuitry on the processor for quick fault detection. To carry out a non‐intrusive, dynamic at‐speed processor testing [12], where the test patterns are applied in the actual operating speed of the processor, software‐based self‐test (SBST) methodologies have been proposed [13–18] and are widely used in the online testing domain.…”