Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements

Abstract

Research on Rent's rule in electrical engineering, the applied sciences, and technology has been based on the publication of a 1971 interpretation of Rent's memoranda by B. S. Landman and R. L. Russo. Because of the wide impact of Rent's work and requests from researchers, we present his original memoranda in this paper. We review the impact of Rent's work and present the memoranda in the context of IBM computer hardware development since the 1950s. Furthermore, because computer hardware components have changed significantly since the memoranda were written in 1960, a new interpretation is needed for today's ultra-large-scale integrated circuitry. On the basis of our analysis of the memoranda, one of the authors' personal knowledge of the 1401 and 1410 computers, and our experience in the design of high-performance circuitry for microprocessor chips, we have derived an historically equivalent interpretation of Rent's memoranda that is suitable for today's computer components. We describe an application of our historically equivalent interpretation to the problem of assessing on-chip interconnection requirements of control logic circuitry in the IBM POWER4e microprocessor.

On brain-inspired hybrid topologies for nano-architectures - a Rent’s rule approach -

“…interpretation of Rent's two internal memoranda from 1960 [14] that introduced his methods (and graphical techniques) to illustrate the relationship between attributes of computer hardware components (for details see also [15] and [16]). …”

“…The 1971 paper of Landman and Russo has been referenced extensively in the literature of several scientific fields, including semiconductor circuitry, computer systems, applied mathematics, applied sciences, and semiconductor manufacturing technology (the interested reader should consult [16] for a very detailed list of applications). One of the most important applications of the 1971 work has been the derivation of models which provide estimates for the wirelength distributions, average wire length, and total interconnection length required to wire chip circuitry correctly [17]- [24].…”

“…Rent's rule has been recently revisited in [15] and [16], and a new interpretation was formulated. Lanzerotti, Fiorenza, and Rand were able to derive a historically-equivalent interpretation of Rent's memos and proved that this is much better suited for today' s computer components.…”

“…Using data from six units in the IBM POWER4 core designs, Lanzerotti, Fiorenza, and Rand plotted on a log-log graph N GATES in each design versus N IO , as well as versus N CONN • Several plots can be seen in [15], [16], and [18] (while a version adapted from [26] is presented in Fig. 1).…”

“…we shall start from exploring the connectivity of the brain, and comparing it to known computer interconnect (network) topologies. For doing these we shall rely on Rent's rule [13], [14], and in particular on a fresh interpretation of Rent's rule reported in [15], [16]. Our aim is to identify those interconnect (network) topologies which could be a better fit for future brain-inspired nanoarchitectures, looking for hybrid (hierarchical) combination of two network topologies which would allow us to optimally approach (mimic) brain's connectivity.…”