MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor

Varchola, Michal; Güneysu, Tim; Mischke, Oliver

doi:10.1109/reconfig.2011.61

Cited by 29 publications

(17 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On the other hand [34,26] have a trade-off between area and time, even though their proposal was aimed and optimized for a different FPGA than ours. In [38] these optimizations become more clear with a lower area and better time results on the Virtex II-Pro platform.…”

Section: Comparisonmentioning

confidence: 99%

“…Sakiyama et al [35] proposed a superscalar coprocessor that could deal with three different curve-based cryptosystems, all in characteristic 2 fields. Varchola et al [38] designed a processor-like architecture, with instruction set and decoder, on top of which they implemented ECC. This approach has the benefit of having a portion written in software, which can be easily maintained and updated, while having special optimized instructions for the elliptic curve operations.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, each of their synthesized circuit would only work for one of the two primes. Pöpper et al [32] follow the same approach as Varchola et al [38], with some side-channel related improvements. The paper focuses on analyze of countermeasures and their effective cost.…”

Section: Introductionmentioning

confidence: 99%

“…Roy et al [34] followed the same path, but with more optimizations with respect to resources and only for curve NIST P-256. However, the number of Block RAMs necessary for the architecture is much larger than of Pöpper et al [32] or Varchola et al [38]. Fan et al [17] created an architecture for special primes and curves, namely the standardized NIST P-192.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Implementing Complete Formulas on Weierstrass Curves in Hardware

Massolino¹,

Renes²,

Batina³

2016

Security, Privacy, and Applied Cryptography Engineering

View full text Add to dashboard Cite

Abstract. This work revisits the recent complete addition formulas for prime order elliptic curves of Renes, Costello and Batina in light of parallelization. We introduce the first hardware implementation of the new formulas on an FPGA based on three arithmetic units performing Montgomery multiplication. Our results are competitive with current literature and show the potential of the new complete formulas in hardware design. Furthermore, we present algorithms to compute the formulas using anywhere between two and six processors, using the minimum number of parallel field multiplications.

show abstract

Section: Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Implementing Complete Formulas on Weierstrass Curves in Hardware

Massolino¹,

Renes²,

Batina³

2016

Security, Privacy, and Applied Cryptography Engineering

View full text Add to dashboard Cite

show abstract

“…At ReConfig 2011, a reconfigurable ECC-p core [29] using a microcode approach [30] was introduced. The design uses a very small arithmetic and logic unit (ALU) and a control unit which is able to read and decode certain instruction sequences from BRAM.…”

Section: Key Exchangementioning

confidence: 99%

IPSecco: A lightweight and reconfigurable IPSec core

Driessen

Güneysu

Mischke

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

Self Cite

View full text Add to dashboard Cite

Abstract-In this paper we propose a reconfigurable lightweight Internet Protocol Security (IPSec) hardware core. Our architecture supports the main IPSec protocols; namely Authentication Header (AH), Encapsulating Security Payload (ESP), and Internet Key Exchange (IKE). In this work, the cryptographic algorithms and their modes of operation, which are at the heart of the IPSec protocols, are implemented in hardware. Instead of re-implementing common IPSec configurations, which are deemed "too heavy" for pervasive devices, we evaluate efficient implementations of standardized and/or well-known lightweight and hardware-friendly algorithms. In particular, we examine different versions of PRESENT, GRØSTL, PHOTON, and a very compact ECC core. As a consequence, we present IPSECCO, a core with adequate security and only moderate resource requirements, making it suitable for lightweight devices. We selected the Xilinx Spartan family of Field Programmable Gate Arrays (FPGA) as target platform due its low-power footprint and reduced costs compared to other FPGAs. Our results show that it is possible to realize a high performance IPSec core even on members of the Spartan-3 family.

show abstract

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high‐speed TRNG based on chaos and ANN implemented in a Xilinx field‐programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan‐Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140‐1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

show abstract

MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor

Cited by 29 publications

References 12 publications

Implementing Complete Formulas on Weierstrass Curves in Hardware

Implementing Complete Formulas on Weierstrass Curves in Hardware

IPSecco: A lightweight and reconfigurable IPSec core

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Contact Info

Product

Resources

About