Methodology to optimize critical node separation in hardened flip-flops

Shambhulingaiah, Sandeep; Chellappa, Srivatsan; Kumar, Sushil; Clark, Lawrence T.

doi:10.1109/isqed.2014.6783364

Cited by 8 publications

(5 citation statements)

References 14 publications

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“…Moreover, they are increasingly susceptible to upset by MNCC, particularly on bulk technologies. The large number of sensitive node groups in the DICE latch also makes it difficult to provide adequate critical node spacing to avoid MNCC induced upsets [16]. Temporal filtering the FF inputs has demonstrated effectiveness when combined with a DICE latch at mitigating both SET and SEU [17].…”

Section: B Hardening Techniquesmentioning

confidence: 99%

“…A meta-program calls an analysis program that in turn runs the HSPICE simulations for maximum flexibility. It is not strictly necessary to run the analysis on all nodes, since combinationally connected nodes are equivalent [16], but it precludes the possibility of an oversight in this key analysis.…”

Section: A Circuit Simulation Based Hardness Verificationmentioning

confidence: 99%

“…The results are tabulated in a dual fault analysis matrix [16]. Single node upsets comprise the diagonal entries and dual fault upsets comprise the lower diagonal.…”

Section: A Circuit Simulation Based Hardness Verificationmentioning

confidence: 99%

“…With minor APR flow modifications, standard cell gates can be automatically placed into the FF gaps using standard tools (e.g., Cadence Encounter) [16]. Given that the CLK block may be adjacent to any other, a conventional single row height hardened design is possible.…”

Section: Ff Layout and Apr Compatibilitymentioning

confidence: 99%

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Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection

Shambhulingaiah

Lieb

Clark

2015

IEEE Trans. Nucl. Sci.

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In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results. Index Terms-Flip-flop, latch, sequential logic circuits, single event transient (SET), single event upset (SEU), soft-errors.

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Section: B Hardening Techniquesmentioning

confidence: 99%

Section: A Circuit Simulation Based Hardness Verificationmentioning

confidence: 99%

“…The results are tabulated in a dual fault analysis matrix [16]. Single node upsets comprise the diagonal entries and dual fault upsets comprise the lower diagonal.…”

Section: A Circuit Simulation Based Hardness Verificationmentioning

confidence: 99%

Section: Ff Layout and Apr Compatibilitymentioning

confidence: 99%

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Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection

Shambhulingaiah

Lieb

Clark

2015

IEEE Trans. Nucl. Sci.

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“…As presented in the previous Section (II-C), the multi-collection is becoming a strong mechanism in very integrated circuit below 28-nm technology (even for SOI technology) and needs to be modeled. However, because of habits, many works consider only the transistor at "off" state and in some cases an unique source of parasite current induced by the radiation on the circuit nodes [86], [87], [89]. This kind of simplified approach leads to limit the real feedback of the circuit.…”

Section: A Toward Integrated "Framework" For Set Modeling In Electromentioning

confidence: 99%

Modeling Single Event Transients in Advanced Devices and ICs

Artola

Gaillardin

Hubert

et al. 2015

IEEE Trans. Nucl. Sci.

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The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.

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