Method of activation energy analysis and application to individual cells of 256Mb DRAM in 110nm technology

Weber, A. C.; Birner, A.; Krautschneider, Wolfgang H.

doi:10.1016/j.sse.2006.03.024

Cited by 15 publications

(4 citation statements)

References 8 publications

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“…This is determined by the SRH generation-recombination current of the reverse-biased n + -channel-p + diode [11]. The extracted EA is close to or higher than half the bandgap corresponding to SRH [12], [13]. In Region Ⅱ, the excess current is sensitive to temperature, which corresponds to the TAT mechanism, where EA is between 0.1 eV and half of the bandgap [14], [15].…”

Section: Resultsmentioning

confidence: 99%

“…Thus, it is logical that the BTBT mechanism from the valence band in the channel to the conduction band in the N + source region was dominant. The temperature dependence of the oncurrent in pTFET arose due to the bandgap reduction with increasing temperature [12], [16], which corresponds to the BTBT mechanism, where EA was below 0.1 eV [12], [17]. Notably, the dominant conduction mechanisms of pTFETs are classified by the extracted EA.…”

Section: Active Trapmentioning

confidence: 99%

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A Study on Dominant Mechanism and Analytical Model of Low-Frequency Noise in FD-SOI pTFET

Shin

Eadi

Kim

et al. 2022

IEEE J. Electron Devices Soc.

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The origin of low-frequency noise (LFN) properties and the accuracy of LFN model were demonstrated in a fully depleted silicon-on-insulator p-type tunneling field-effect transistor (pTFET). We demonstrated that the origin of LFN properties in pTFET can be deduced and analyzed via the current fluctuation induced by tunneling in the pTFET operation region. Since the trap sites near the tunneling junction contributed to LFN, pTFET must consider the tunneling junction characteristics and channel transportation influences. The tunneling path was not formed at low |VGS| and the carrier transport in pTFET crossed the energy band by Shockley-Read-Hall (SRH) generation-recombination or the trap-assisted tunneling (TAT) mechanism and not through band-to-band tunneling (BTBT). However, with the increase in |VGS|, the tunneling path was formed and the carriers could flow through the energy band by BTBT. The correlation between the simulated model data and experimental data was examined, confirming that the proposed small-signal model accurately represents noise in pTFETs.

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Section: Resultsmentioning

confidence: 99%

Section: Active Trapmentioning

confidence: 99%

A Study on Dominant Mechanism and Analytical Model of Low-Frequency Noise in FD-SOI pTFET

Shin

Eadi

Kim

et al. 2022

IEEE J. Electron Devices Soc.

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“…Temperature and voltage accelerations need to be studied in order to model Tret degradation. Tret degradation is a complex process with multiple mechanisms involved [2]. These mechanisms include: (1) sub-threshold leakage current of transfer transistor; (2) capacitor dielectric leakage current;…”

Section: Test3mentioning

confidence: 99%

A study of scaling effects on DRAM reliability

White

Qin

Bernstein

2011

2011 Proceedings - Annual Reliability and Maintainability Symposium

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In this study, commercial 512Mb Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) modules from three progressive technologies130nm, 110nm and 90nm -were selected for experimentation to investigate degradation trends as a function of scaling. High temperature, high voltage accelerated stress testing was performed to characterize DRAM reliability and failure rates. Retention time degradation over time as a function of stress was also studied.For each technology generation, two distinct soft error populations were observed: Tail Distribution, characterized by randomly distributed weak bits with Weibull slope =1, and Main Distribution with Weibull slope greater than 1. Retention time was found to degrade exponentially with time. Analysis reveals multiple failure mechanisms are involved in retention time degradation. Activation energy was found to change with stress temperature for all three technologies.There are several observations with regard to scaling effects on DRAM reliability. First, the smaller the technology, the larger the operating current increases in percentage after high temperature, high voltage accelerated stress. Second, cell retention time variation decreases as technology scales down. Third, 90nm DRAM has the largest soft-error failure rate among three technologies under equivalent stress, 110nm DRAM has better reliability performance than 130nm at 55°C and 75°C, and 130nm DRAM is the best at 125°C. Studies continue into the scaling effects on reliability of progressive DRAM technologies.

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“…A higher E a value corresponds to a higher sensitivity of I Leak on temperature. E a can be experimentally obtained by measurement of the retention time of individual memory cells at different temperatures (see [6] for details). Measured values can be compared with theoretically calculated activation energies of different leakage mechanisms.…”

Section: Activation Energymentioning

confidence: 99%

Retention Tail Improvement for Gbit DRAMs through Trap Passivation confirmed by Activation Energy Analysis

Weber¹,

Birner²,

Krautschneider

2006

2006 European Solid-State Device Research Conference

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A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM data retention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electric fields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512Mbit and 1Gbit DRAMs in 110 nm technology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retention tail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40 %. Detailed activation energy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps by fluorine implantation.

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Method of activation energy analysis and application to individual cells of 256Mb DRAM in 110nm technology

Cited by 15 publications

References 8 publications

A Study on Dominant Mechanism and Analytical Model of Low-Frequency Noise in FD-SOI pTFET

A Study on Dominant Mechanism and Analytical Model of Low-Frequency Noise in FD-SOI pTFET

A study of scaling effects on DRAM reliability

Retention Tail Improvement for Gbit DRAMs through Trap Passivation confirmed by Activation Energy Analysis

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