Metastability in CMOS library elements in reduced supply and technology scaled applications

Portmann, C.; Meng, Huo

doi:10.1109/4.350196

Cited by 51 publications

(11 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In this paper a voltage model is adopted [11], in order to relate τ to FO4 delay, a principal scaling indicator. Correlation to models based on current using g m [12] [13] can also be shown.…”

Section: Modeling τ τ τ τmentioning

confidence: 99%

The devolution of synchronizers

Beer¹,

Ginosar

Priel

et al. 2010

2010 IEEE 26-Th Convention of Electrical and Electronics Engineers in Israel

View full text Add to dashboard Cite

Section: Modeling τ τ τ τmentioning

confidence: 99%

The devolution of synchronizers

Beer¹,

Ginosar

Priel

et al. 2010

2010 IEEE 26-Th Convention of Electrical and Electronics Engineers in Israel

View full text Add to dashboard Cite

“…The simulation setup is similar to that described in Portmann and Meng (1995) . The data arrival time is changed with respect to a ® xed clock edge, as shown in ® gure 3.…”

Section: Methodsmentioning

confidence: 99%

“…An idealized plot of a CMOS latch' s resolution time versus the data arrival is shown in ® gure 2 (Sakurai 1988, Portmann andMeng 1995). When data arrive before t meta , the data will be latched.…”

Section: Introductionmentioning

confidence: 99%

Metastability of SOI CMOS latches

Tretz¹,

Chuang²,

Terman³

et al. 1999

International Journal of Electronics

View full text Add to dashboard Cite

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide± silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbu ered latch. The metastability window, resolution time and time interval between the clock edge and the time t meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI speci® c body-connection topologies.

show abstract

“…Metastability is the phenomenon where a bistable element requires an indeterminate amount of time to generate a valid output [34]. The metastability in a latch comparator occurs when the differential input signal is so small that the latch does not have enough time to produce a well-defined logic level, which might be interpreted differently by succeeding logic, leading to conversion errors.…”

Section: Metastabilitymentioning

confidence: 99%

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

View full text Add to dashboard Cite

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

show abstract

Metastability in CMOS library elements in reduced supply and technology scaled applications

Cited by 51 publications

References 16 publications

The devolution of synchronizers

The devolution of synchronizers

Metastability of SOI CMOS latches

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Contact Info

Product

Resources

About