Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Abstract

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

A novel analog switch for high‐precision switched‐capacitor applications

“…Apart from the settling error, the maximum permissible input frequency will also impose a limitation on the 3-dB bandwidth of the mentioned resistor-capacitor structure. By considering these requirements, the minimum required tracking bandwidth 21 should satisfy the Equation 16:…”

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

“…A technique to overcome this limitation is to remove the dummy C u in the sub DAC such that C B = C u [24]. However this causes a gain error of 1/1 − 2 −N [25] which can be calibrated in the digital domain if needed. It is shown in [26] that the parasitic capacitance C P,A causes code-dependent errors and thus degrades linearity of the ADC.…”

“…For capacitor matching, the mid-code transition is considered as the worst case, since all the capacitors in the BWC DAC are switched. For an N -bit SAR ADC, the maximum DNL error should be limited to [61], [27] …”

Design of an ultra low-power CMOS analog-to-digital converter for biomedical applications

“…The lower bound of the conventional SAR ADC power consumption has been well studied [11,[23][24][25][26]. In [11], the energy models were developed for high-speed architecture by assuming the comparator model as a pre-amplifier with a latch.…”

“…In [11], the energy models were developed for high-speed architecture by assuming the comparator model as a pre-amplifier with a latch. The analysis in [23][24][25][26] took a better understand in the modern deep-submicron technologies. However, the comparator was assumed to be a simple one-stage latched comparator.…”