Metastability characterization for muller C-elements

Polzer, Thomas; Steininger, Andreas

doi:10.1109/patmos.2013.6662170

Cited by 6 publications

(6 citation statements)

References 13 publications

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“…3 is used to synchronize "grt" and "clk_rd" signals, and to make sure the minimum pulse width of the clock signal. The basic operation of the Muller-C is described in [13]. …”

Section: Mutex In a Pausible Clocking Based Gals Systemmentioning

confidence: 99%

Measurements of metastability in MUTEX on an FPGA

Toan

Tung

Lee

2018

IEICE Electron. Express

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In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).

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“…3 is used to synchronize "grt" and "clk_rd" signals, and to make sure the minimum pulse width of the clock signal. The basic operation of the Muller-C is described in [13]. …”

Section: Mutex In a Pausible Clocking Based Gals Systemmentioning

confidence: 99%

Measurements of metastability in MUTEX on an FPGA

Toan

Tung

Lee

2018

IEICE Electron. Express

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“…5 Again, in a closed asynchronous design that respects the indication principle such conditions will never occur. 6 For MCE implementation di®erent circuits have been proposed, each of which coming with di®erent bene¯ts and drawbacks.…”

Section: Sequential Elements For Asynchronous Environmentsmentioning

confidence: 99%

“…However, as we have shown previously, the late transition detection circuit can be carefully adapted to this purpose. 8,5 Another fundamental sequential function block is the RS-latch. Its function is to set the output to HI when its set input is activated, and to set it to LO when its reset input is activated.…”

Section: Sequential Elements For Asynchronous Environmentsmentioning

confidence: 99%

A Model for the Metastability Delay of Sequential Elements

Polzer

Steininger

2017

J CIRCUIT SYST COMP

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It is well known that every sequential element may become metastable when provided with marginal inputs, such as input transitions occurring too close or input voltage not reaching a de¯ned HI or LO level. In this case the sequential element requires extra time to decide which digital output level to¯nally present, which is perceived as an output delay. The amount of this delay depends on how close the element's state is to the balance point, at which the delay may, theoretically, become in¯nite. While metastability can be safely avoided within a closed timing domain, it cannot be completely ruled out at timing domain boundaries. Therefore it is important to quantify its e®ect. Traditionally this is done by means of a \mean time between upsets" (MTBU) which gives the expected interval between two metastable upsets. The latter is de¯ned as the event of latching the still undecided output of one sequential element by a subsequent one. However, such a de¯nition only makes sense in a time-safe environment like a synchronous design. In this paper we will extend the scope to so-called value-safe environments, in which a sequential element can safely¯nalize its decision, since the subsequent one waits for completion before capturing its output. Here metastability is not a matter of \failure" but a performance issue, and hence characterization by MTBU is not intuitive. Therefore we will put the focus on the delay aspect and derive a suitable model. This model extends existing approaches by also including the area of very weak metastability and thus providing complete coverage. We will show its validity through comparison with transistor-level simulation results for the most popular sequential elements in di®erent implementations, point out its relation to the traditional MTBU model parameters, namely and T 0 , and show how to use it for calculating the performance penalty in a value-safe environment.

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“…The MCE becomes metastable [3] when an output transition is triggered but then withdrawn before being completed, which can happen for coincident contradicting input transitions and for short input pulses. Again, in a closed asynchronous design that respects the indication principle [4] such conditions will never occur.…”

Section: Sequential Elements For Asynchronous Environmentsmentioning

confidence: 99%

“…However, as shown in [6], [3], the late transition detection circuit can be carefully adapted to this purpose.…”

Section: Sequential Elements For Asynchronous Environmentsmentioning

confidence: 99%

A general approach for comparing metastable behavior of digital CMOS gates

Polzer

Steininger

2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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In digital CMOS essentially all sequential function blocks may get metastable in one way or another, when provided with marginal inputs. Most often the result is a delayed reaction at the output, which, in a synchronous design, potentially violates the timing assumptions. Therefore metastable behavior is often characterized by the Mean Time Between Upset (MTBU), which reflects the expected interval between such violations on a statistical base.However, not all designs are synchronous -there are even sequential elements specifically intended for use in context with elastic timing, such as the mutual exclusion element or the Muller C-element. For these a characterization via MTBU is not useful; but on the other hand there seem to be no reasonable alternatives. Therefore in this paper we propose the use of the delay graph (over the relevant quantity that causes metastability when becoming marginal) for this purpose. We elaborate its correspondence with the usual MTBU graph and the metastability parameters, namely tau and T0. As a proof of concept we apply our strategy to a set of sequential elements, like D-latch, RS-latch, Muller Celement and mutex and discuss the differences we identified.

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Metastability characterization for muller C-elements

Cited by 6 publications

References 13 publications

Measurements of metastability in MUTEX on an FPGA

Measurements of metastability in MUTEX on an FPGA

A Model for the Metastability Delay of Sequential Elements

A general approach for comparing metastable behavior of digital CMOS gates

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