A general approach for comparing metastable behavior of digital CMOS gates

Abstract

In digital CMOS essentially all sequential function blocks may get metastable in one way or another, when provided with marginal inputs. Most often the result is a delayed reaction at the output, which, in a synchronous design, potentially violates the timing assumptions. Therefore metastable behavior is often characterized by the Mean Time Between Upset (MTBU), which reflects the expected interval between such violations on a statistical base.However, not all designs are synchronous -there are even sequential elements specifically intended for use in context with elastic timing, such as the mutual exclusion element or the Muller C-element. For these a characterization via MTBU is not useful; but on the other hand there seem to be no reasonable alternatives. Therefore in this paper we propose the use of the delay graph (over the relevant quantity that causes metastability when becoming marginal) for this purpose. We elaborate its correspondence with the usual MTBU graph and the metastability parameters, namely tau and T0. As a proof of concept we apply our strategy to a set of sequential elements, like D-latch, RS-latch, Muller Celement and mutex and discuss the differences we identified.

A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements

“…The role of metastability filter is to prevent the MUTEX outputs Q 1 and Q 2 from metastable states at the outputs O 1 and O 2 of the RS latch. The metastable states in the RS latch occur when the both edges ( S and R ) come to the inputs of the MUTEX block almost at the same time [ 46 ]. Then, the RS latch requires a long time to decide which edge arrived first, and is reflected by the metastable state on O 1 and O 2 ( Figure 26 a).…”