Metamorphic InyGa1−yAs/InzAl1−zAs heterostructure field effect transistors grown on GaAs(001) substrates using molecular-beam epitaxy

Abstract

Electrical characterization of pseudomorphic GaAs/InGaAs/AlGaAs and AlGaAs/InGaAs/AlGaAs modulation doped field effect transistortype heterostructures grown by molecularbeam epitaxy

Low-Temperature and Metamorphic Buffer Layers

“…Step-graded device structures typically exhibit cross-hatch morphology with corrugations along the [110] and ½110 directions [20], as shown in the optical micrograph of Figure 25.5 for a mid-IR laser diode on an InP (001) substrate with a step-graded InAs y P 1Ày buffer layer [29]. It has been shown that the average period of surface undulations corresponds approximately to the separation of misfit dislocations, projected into the interface and observed by PVTEM [76].…”

“…Grider et al [20] showed that, for In x Ga 1Àx As HEMTs (0.2 x 0.5) grown on GaAs substrates by MBE with a step-graded In x Ga 1Àx As buffer, low-temperature buffer growth at 300 C resulted in a structure in which threading dislocations were confined to the buffer and the 77 K electron mobility was >22,000 cm 2 V À1 s À1 at x ¼ 0.4. Grider et al [20] showed that, for In x Ga 1Àx As HEMTs (0.2 x 0.5) grown on GaAs substrates by MBE with a step-graded In x Ga 1Àx As buffer, low-temperature buffer growth at 300 C resulted in a structure in which threading dislocations were confined to the buffer and the 77 K electron mobility was >22,000 cm 2 V À1 s À1 at x ¼ 0.4.…”

“…The metamorphic approach, in which layers of the structure relax partially by the introduction of misfit dislocations, allows great flexibility in choosing compositions and thicknesses of semiconductor layers [20]. The key to successful realization of a metamorphic semiconductor device structure is the design of an appropriate buffer layer which can relax the lattice mismatch existing between the substrate and device.…”

“…The threading dislocation density is determined by cross-sectional transmission electron microscopy (XTEM) [20,28,29], plan-view transmission electron microscopy (PVTEM) [2], high-resolution X-ray diffraction [30], or etch pit density measurements [2]. Moreover, its properties are not compromised by the subsequent growth of device layers.…”

Electric Circuit Model Analogy for Equilibrium Lattice Relaxation in Semiconductor Heterostructures

“…[1][2][3][4][5][6] Furthermore, the equilibrium configuration serves as the starting point for kinetically-limited lattice relaxation calculations and is critical in determining the effective stress and therefore the driving force for dislocation flow. Several models have been developed for the determination of the equilibrium configuration [7][8][9][10][11][12][13][14][15] and, although it has been shown that the equilibrium configuration for a general semiconductor strained-layer structure may be determined numerically by energy minimization using an appropriate partitioning of the structure into sublayers, [7][8][9][10][11] such an approach uses specialized code, is computationally intense, and does not lend itself to an intuitive understanding necessary for innovative structure design.…”