Metallic doping: a new strategy for suppressing shallow-trap centers in vertically stacked charge-trapping flash memories

Wang, Fei; Wu, Jixuan; Li, Yuan; Cao, Rui; Chen, Jiezhi

doi:10.35848/1882-0786/ab7e0b

Cited by 6 publications

(8 citation statements)

References 23 publications

(24 reference statements)

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“…We turn to consider the impact of metallic doping, such as Ti doping, which was proved to be efficient in Si3N4 for suppressing the shallow-trap centers in 3D NAND [12]. During this process, Ti-doping could easily take place in Si2N2O.…”

Section: A Defects-induced Lateral Charge Lossmentioning

confidence: 99%

“…In the case of Ti-doped systems, as shown in Fig. 6(d), the intrinsic trap centers in Si3N4 are replaced by defects with Ti doping, such as the 2.12 eV Tii (Et ~ 0.88 eV) and 1.57 eV TiSi (Et ~ 1.43 eV) defects serving as electron trap centers [12]. As discussed above, the electrons stored in the Tii and TiSi defects in Si3N4 could tunnel to the Ti-related defects in Si2N2O because of the resonance of the trap energy.…”

Section: B Defects-induced Vertical Charge Lossmentioning

confidence: 99%

“…In particular, lateral charge migration between adjacent cells can lead to read disturb (RD) and data retention (DR), [10][11] which issues could be much more serious with size scaling. As such, several approaches, such as metallic doping [12] and process optimization [13], were proposed to suppress charge migration in 3D CT NAND flash memory. As one of the most frequently used methods, process optimization could greatly improve device reliability by reducing defects at the interface to guarantee the purity of Si3N4.…”

Section: Introductionmentioning

confidence: 99%

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Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Wang

et al. 2021

IEEE Access

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In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss. Here, by first-principles calculations, we present a detailed study on the defects in the transition layer Si2N2O to comprehend their impacts on charge loss in CT 3D NAND flash memory. It is shown that shallow-trap centers, such as intrinsic nitrogen vacancy (VN) and interstitial Ti (Tii), can couple with the conduction band of Si2N2O to lead to lateral charge loss. On the other hand, the N substituting Si atom (NSi) and Ti substituting Si atom (TiSi) defects in the transition layer can couple through resonance with the trap centers in Si3N4, leading to vertical charge loss from the CT layer to the transition layer. Our results strongly suggest that appropriate treatment of the transition layer and hydrogen passivation are both important for avoiding charge loss in CT 3D NAND flash memory.

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Section: A Defects-induced Lateral Charge Lossmentioning

confidence: 99%

Section: B Defects-induced Vertical Charge Lossmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Wang

et al. 2021

IEEE Access

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“…Thus, larger grain size and higher o-HfO 2 content can be achieved. 34 However, with further increase in Al content, the density of V O 2+ decreased to 10 11 cm −3 instead of continuously increasing because the formation of a large amount of 2Al Hf 2+ increased the Fermi energy level and resulted in higher formation energy of . Meanwhile, the density of 2Al Hf 2+ and Al Hf − increased to 10 22 cm −3 , which was too high for doping.…”

mentioning

confidence: 97%

“…Higher Al content induced greater mechanical force to stabilize the o-phase and adjusted the Fermi energy level, which contributed to the formation of V O 2+ . Thus, larger grain size and higher o-HfO 2 content can be achieved …”

mentioning

confidence: 99%

The Doping Effect on the Intrinsic Ferroelectricity in Hafnium Oxide-Based Nano-Ferroelectric Devices

Wei

Meng

et al. 2023

Nano Lett.

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Hafnium oxide (HfO 2 )-based ferroelectric tunnel junctions (FTJs) have been extensively evaluated for high-speed and low-power memory applications. Herein, we investigated the influence of Al content in HfAlO thin films on the ferroelectric characteristics of HfAlO-based FTJs. Among HfAlO devices with different Hf/Al ratios (20:1, 34:1, and 50:1), the HfAlO device with Hf/Al ratio of 34:1 exhibited the highest remanent polarization and excellent memory characteristics and, thereby, the best ferroelectricity among the investigated devices. Furthermore, first-principal analyses verified that HfAlO thin films with Hf/Al ratio of 34:1 promoted the formation of the orthorhombic phase against the paraelectric phase as well as alumina impurities and, thus, enhanced the ferroelectricity of the device, providing theoretical support for supporting experimental results. The findings of this study provide insights for developing HfAlO-based FTJs for next-generation in-memory computing applications.

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Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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Metallic doping: a new strategy for suppressing shallow-trap centers in vertically stacked charge-trapping flash memories

Cited by 6 publications

References 23 publications

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

The Doping Effect on the Intrinsic Ferroelectricity in Hafnium Oxide-Based Nano-Ferroelectric Devices

Review of Semiconductor Flash Memory Devices for Material and Process Issues

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