Metal-oxide-high-k-oxide-silicon memory structure incorporating a Tb2O3 charge trapping layer

Pan, Tung-Ming; Jung, Ji-Shing; Chen, Fa-Hsyang

doi:10.1063/1.3462321

Cited by 23 publications

(11 citation statements)

References 15 publications

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“…The aforementioned analysis is also evidenced by the P/E transient characteristics for all kinds of CTLs shown in Fig. 22 from which the stacked ZnO/NiO CTL manifests the best performance in terms of memory window of 1.32 V and 1.88 V respectively obtained by for programing and erasing at ±4 V for 1 ms. With an operation time of 1 ms, compared with other high-k CTL such as ZrO2 [38], multiple Ta2O5 [39], Tb2O3 [40] and SrTiO3 [41], the stacked ZnO/NiO CTL can achieve comparable memory window at much lower voltage of 4 V. The performance also proves the merit of employing a ZnO/NiO CTL to implement low-power green memory devices. As the program and erase voltage increases to ±5 V for 1 ms, memory window respectively become 1.73 V and 2.12 V (not shown).…”

Section: Trapping Layermentioning

confidence: 68%

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Chen

Teng

Chang

et al. 2016

IEEE J. Electron Devices Soc.

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Journal of the Electron Devices Society 6 V. CONCLUSION With incumbent flash memory devices operated in the range of 15-17 V, it is imperative to pursue green flash memory that can be operated at voltage less than 10 V to realize a sustainable environment. In this paper, two promising CTL types based on crystalline oxide including crystalline high-k dielectric and crystalline oxide semiconductor which possess the capability to achieve this goal are reviewed. For CTL based on crystalline high-k dielectric, the distinct advantage for memory operation is the k value higher than 30 which is much higher than the amorphous counterpart and beneficial to reduce operation voltage since a higher effective electric field can be exerted on the tunnel SiO2 due to electric flux density continuity. The most concerned retention issue of adopting a crystalline high-k CTL has also be circumvented by passivation of grain boundaries related defects through plasma treatment. The concept of employing crystalline high-k dielectric as CTL not only works for Si-channel flash memory but also Ge-channel memory devices which enable superior memory performance to Si-based counterpart due to higher carrier mobility and more desirable band structure. For CTL based on crystalline oxide semiconductor, a CTL formed by stacking n-type and p-type oxide semiconductor demonstrates typical diode characteristics with a built-in internal electric field. It is the unique internal field that enhances P/E speed while reducing the operation voltage. Both kinds of CTL create a differentiating and pioneering technology that gains an outlook on realizing green flash memory devices.

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Section: Trapping Layermentioning

confidence: 68%

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Chen

Teng

Chang

et al. 2016

IEEE J. Electron Devices Soc.

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“…Among them, Tb 2 O 3 possesses desirable properties for charge trap Flash device application, such as a relatively high dielectric constant, a large band gap, a large conduction band offset with regard to silicon and good thermal stability with Si. A metal-oxide-high-k-oxide-silicon (MOHOS)-type memory structure fabricating a high- k Tb 2 O 3 charge-trapping layer for flash memory applications was reported afterwards [ 44 ]. The high- k Tb 2 O 3 MOHOS-type memories annealed at 800 °C exhibited large threshold voltage shifting (memory window of 1.41 V operated at V g = 8 V at 0.1 s), excellent data retention (charge loss of 10% measured time up to 10 4 s and at 85 °C), and good endurance characteristics (program/erase cycles up to 10 5 ) because of the high probability and deep trap level for trapping the charge carrier due to the formation of the crystallized Tb 2 O 3 with a high dielectric constant of 11.8.…”

Section: Recent Developmentsmentioning

confidence: 99%

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm

et al. 2014

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Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly.

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“…As mentioned previously, crystalline dielectric has been adopted as the charge trapping layer6789101112 and even blocking oxide1042. Since the crystalline dielectrics used in the devices are of poly-crystalline phase, one concern may be the variation of number of grains in a cell which would lead to undesirable non-uniformity of device performance.…”

Section: Resultsmentioning

confidence: 99%

“…However, most high-k based CTLs are of amorphous phase with their k values rarely exceeding 25, limiting further scaling in operation voltage. Recently, phase transformation of a high-k dielectric from amorphous phase to crystalline one has attracted considerable interest since it provides an effective method to enhance the k value without compromising the bandgap6789101112. The widely developed crystalline CTL mainly focuses on ZrO 2 6789 with a k value of 38.7 in tetragonal phase6 and 32.8 in cubic phase8.…”

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confidence: 99%

Flash Memory Featuring Low-Voltage Operation by Crystalline ZrTiO4 Charge-Trapping Layer

Shen

Chen

et al. 2017

Sci Rep

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Crystalline ZrTiO4 (ZTO) in orthorhombic phase with different plasma treatments was explored as the charge-trapping layer for low-voltage operation flash memory. For ZTO without any plasma treatment, even with a high k value of 45.2, it almost cannot store charges due the oxygen vacancies-induced shallow-level traps that make charges easy to tunnel back to Si substrate. With CF4 plasma treatment, charge storage is still not improved even though incorporated F atoms could introduce additional traps since the F atoms disappear during the subsequent thermal annealing. On the contrary, nevertheless the k value degrades to 40.8, N2O plasma-treated ZTO shows promising performance in terms of 5-V hysteresis memory window by ±7-V sweeping voltage, 2.8-V flatband voltage shift by programming at +7 V for 100 μs, negligible memory window degradation with 105 program/erase cycles and 81.8% charge retention after 104 sec at 125 °C. These desirable characteristics are ascribed not only to passivation of oxygen vacancies-related shallow-level traps but to introduction of a large amount of deep-level bulk charge traps which have been proven by confirming thermally excited process as the charge loss mechanism and identifying traps located at energy level beneath ZTO conduction band by 0.84 eV~1.03 eV.

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Metal-oxide-high-k-oxide-silicon memory structure incorporating a Tb2O3 charge trapping layer

Cited by 23 publications

References 15 publications

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm

Flash Memory Featuring Low-Voltage Operation by Crystalline ZrTiO4 Charge-Trapping Layer

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