Metal gates for advanced CMOS technology

Abstract

This paper will provide an overview of the emerging trends in metal gate solutions for advanced CMOS technology. Performance enhancement in silicon-based CMOS technology through MOSFET scaling has shown some limitations with the current polysilicon gate electrode. Replacing polysilicon gate electrode by metal appears to be promising. However, the choice of the metal gate material depends on its work function (single or dual metal gates), thermal/chemical stability with surrounding materials, process integration (conventional or inlaid approach), deposition process, resistivity, and eventually performance, reliability and future scaling. This paper will discuss some of the results published in the literature that address some of these issues and propose future directions. Single mid-gap metal gate approach appears to be simpler from an integration point of view but achieving low MOSFET threshold voltage is a concern. Some channel engineering approaches have been reported to address this issue. Dual metal gate approach with work function similar to n and p doped poly-Si appears ideal, although processing complexity could be a hindrance. Also the need for inlaid gate integration could be enhanced because of thermal/chemical stability effects of metal gate electrode with underlying gate dielectric, the inability to etch new materials or to reduce device instability due to film stress as in the conventional approach. The performance improvement of CMOS devices has been estimated with metal gates along with reliability issues.

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

“…The vertical field strength can be improved either with the application of gate material with higher work function or by reducing the gate dielectric thickness. Applying the gate material with a higher work function has been reported as a poor choice due to associated process integration challenges [9]. On the other hand, reduction in dielectric thickness leads to increased gate-leakage current which has been taken care-off with the introduction of high-k dielectrics such as hafnium oxide (HfO 2 ) [10].…”

The Work Function Behavior of Aluminum-Doped Titanium Carbide Grown by Atomic Layer Deposition

“…Accordingly, the conformal deposition of the gate electrode along the 3-D structure and precise control over its work function has become essential requirements in deep-scaled logic devices [1], [2]. These requirements render the conventional metal sputtering process unsuitable [3], [4], and they demand the use of a metal atomic layer deposition (ALD) process as it provides atomic scale controllability and conformability.…”

Nb and NbN Metal Gates for Gate Stacks with High-k Dielectrics

“…The aggressive scaling according to the ITRS Roadmap requires new solutions for the MOS gate stack [1,2]. One of the topics is the integration of metal gate electrodes in order to avoid gate depletion effects known from poly-Si gates, to provide significantly smaller sheet resistance for smaller gate delay [3], and to avoid incompatibilities of poly-Si gates with high-k dielectrics [4].…”