Mesa-sidewall gate leakage in InAlAs/InGaAs heterostructure field-effect transistors

Bahl, S.R.; Leary, M.; Alamo, J.A. del

doi:10.1109/16.155875

Cited by 45 publications

(19 citation statements)

References 21 publications

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“…Both effects are not desirable in low noise and power device applications. In addition, sidewall leakages were found to worsen with higher doping, increased channel thickness, and increased x (x > 0.53) in InxGa1-xAs channel [13].…”

Section: Sidewall Spacermentioning

confidence: 99%

“…The gate metal running up the MESA side is depicted in Figure 5. The gate metal in contact with the InGaAs channel will form a complete sidewall-gate leakage path from gate to channel [13][14][15]. Although the metal-channel contact area is very small several orders smaller than the gate area, the low Schottky barrier height of metals with narrow band gap InGaAs channel potentially results in a notable leakage whose path runs from the gate to the channel.…”

Section: Sidewall Spacermentioning

confidence: 99%

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Gate recess study for high thermal stability pHEMT devices

et al. 2017

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Abstract. Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky's gate leakage on 1 µm gate pHEMT device. In our study, we found that low sintering temperatures of 200 C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky's gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.

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Section: Sidewall Spacermentioning

confidence: 99%

Section: Sidewall Spacermentioning

confidence: 99%

Gate recess study for high thermal stability pHEMT devices

et al. 2017

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“…39,40 Due to the sidewalls created during wet etching, it is hard to prevent the gate metal from overlapping the mesa edge thus creating a parasitic leakage path to the channel 42 …”

Section: Fabrication Proceduresmentioning

confidence: 99%

“…This may be attributed to the parasitic leakage path along the mesa edge. 42 Ion implant will be needed to improve the isolation. …”

Section: Characteristics Of Fabricated Mosfetsmentioning

confidence: 99%

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

Hall¹,

Fay²,

Kosel³

et al. 2006

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Executive Summary of AccomplishmentsOur research project entitled "Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides" was focused primarily on developing and understanding InAlP wet thermal native oxides for GaAs-based electronic devices and yielded the following notable results:• First demonstration of microwave-frequency operation of a GaAs metal-oxidesemiconductor field-effect transistor (MOSFET) fabricated using wet thermal oxidization of InAlP lattice-matched to GaAs to form a native oxide gate insulator. For 1-µm gate length devices, a cutoff frequency (f t ) of 13.7 GHz and a maximum frequency of oscillation (f max ) of 37.6 GHz were obtained [1].• Follow-on use --Technology Assist: Notre Dame has negotiated a collaborative research agreement with RF Micro Devices, Inc. (Greensboro, NC) to investigate potential of III-V compound semiconductor native oxides for commercial GaAs-based MOSFET devices.• First demonstration of scalability of InAlP to thinner (~10-20 nm) films more suitable for devices, maintaining excellent insulating and unpinned interface properties. Extremely low leakage current densities observed even for these device-thickness films, with values comparable and often lower than that of other candidate GaAs gate dielectrics [2].• First reported III-V metal-oxide-semiconductor field-effect transistor (MOSFET) device utilizing native oxide of InAlP as the gate insulator [3].• Observation via Transmission Electron Microscopy (TEM) imaging that interfacial precipitates, which decrease in size with decreasing oxidation time, are completely absent in ~20 nm thick oxide films. Identification of precipitates as In rich [2, 6].• Development of new variable-temperature impedance spectroscopy measurement technique to determine low total interface state density of D it = 8 x 10 11 cm -2 for a 110 nm thick InAlP native oxide film. Trap activation energies were found (E a =0.17 eV from bias-dependent impedance spectra, 0.40 eV from measurements of temperaturedependent impedance spectra [4, 7].• Identification via transmission electron microscopy analysis in diffusion marker experiment of inward growth of InAlP native oxide, key to achieving electrically clean oxide/semiconductor interfaces [5].• Determination of InAlP native oxide bandgap (≥ 4.0 eV) and optical constants [2, 6].• Determination of mass density of InAlP native oxide films via X-ray reflectivity measurements. The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing the burden, to the Department of Defense, Executive Services and Communications Directorate (0704-0188). Respondents should be aware that notwithstanding any other provision of...

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“…5. In addition, the gate leakage current observed in MOS-PHEMT comes from a gate leakage path at the edge of the mesa [22] that is not present in the MOS capacitor, which may contribute to the Schottkylike I-V characteristics for forward biases. Fig.…”

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confidence: 99%

Liquid Phase Oxidation on InGaP and Its Applications

Wang¹,

Lee²

2010

Advances in Solid State Circuit Technologies

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IntroductionHigh-electron-mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) have attracted many attentions in high speed and power applications due to the superior transport properties. As compared to AlGaAs pseudomorphic HEMTs (PHEMTs), InGaPrelated devices have advantages, such as higher band gaps, higher valence-band discontinuity [1], negligible deep-complex (DX) centers [2], excellent etching selectivity between InGaP and GaAs, good thermal stabilities [3][4][5], higher Schottky barrier heights [3], and so on. Particularly, the use of an undoped InGaP insulator takes the advantages of its low DX centers and low reactivity with oxygen [6-10], which may still suffer from the high gate leakage issue. In order to inhibit the gate leakage issue, increase the power handling capabilities, and improve the breakdown voltages, a metal-oxide-semiconductor (MOS) structure has been widely investigated. However, it is still lacks a reliable native oxide film growing on InGaP, and very few papers have reported on InGaP/InGaAs MOS-PHEMTs. In addition, the MOS-PHEMT not only has the advantages of the MOS structure (e.g., lower leakage current and higher breakdown voltage) but also has the high-density, high-mobility 2DEG channel. Over the past years, a study on the liquid phase oxidation (LPO) of InGaP near room temperature has been done [11][12][13][14]. The application of surface passivation to improve the InGaP/GaAs HBTs' performance has also been first demonstrated [13]. The InGaP/GaAs HBTs with surface passivation by LPO exhibit significant improvement in current gain at low collector current regimes due to the reduction of surface recombination current, as compared to those without surface passivation. Moreover, a larger breakdown voltage and a lower base recombination current are also obtained. In this chapter, the oxide film composition and some issues are addressed. Then a thin InGaP native oxide film prepared by the LPO as the gate dielectric for InGaP/InGaAs MOS-PHEMTs application are discussed, and the comparisons between devices with and without LPO passivation on the InGaP/GaAs HBTs are also reviewed.

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Mesa-sidewall gate leakage in InAlAs/InGaAs heterostructure field-effect transistors

Cited by 45 publications

References 21 publications

Gate recess study for high thermal stability pHEMT devices

Gate recess study for high thermal stability pHEMT devices

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

Liquid Phase Oxidation on InGaP and Its Applications

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