Merits of heat assist for melt laser annealing

Shibahara, Kentaro; Eto, Takanori; Kurobe, Ken-ichi

doi:10.1109/ted.2006.871870

Cited by 5 publications

(6 citation statements)

References 16 publications

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“…There are recent studies that indicate that these technologies could be equivalent to current technologies from a transistor stand-point (7). While one technique capitalizes on solid-phase epitaxy (microwave annealing), the other one relies on the highest form of non-equilibrium or metastable heating in order to freeze the dopants in the lattice (melt annealing) (9,10,11).…”

Section: Introductionmentioning

confidence: 99%

(Invited) Advanced (Millisecond) Annealing in Silicon Based Semiconductor Manufacturing

et al. 2010

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Rapid thermal annealing has taken a new turn at the beginning of this century with the advent of term "advanced annealing". Although the annealing techniques are a few decades old, they have not seen many applications in the semiconductor industry until recently, primarily due to the complexity of the tools involved and their mechanical interaction with silicon wafers. The tolerance for dopant diffusion has reduced significantly from one ITRS node to next. Advanced anneals rely primarily on achieving super-high temperatures (>1100oC) in very short periods of time (milliseconds). These anneals provide the relevant thermal budget for dopant activation processes with minimal diffusion, thus making them attractive. However, as process integration has become more complex additional challenges are encountered by super-high temperature anneals at the recent technology nodes. Additionally, these annealing techniques impart severe mechanical stress on wafers by heating the wafers at rates >10^5 oC/s. This paper will focus on simulation and experimental verification of stress that is experienced by silicon wafers during a millisecond annealing process

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Section: Introductionmentioning

confidence: 99%

(Invited) Advanced (Millisecond) Annealing in Silicon Based Semiconductor Manufacturing

et al. 2010

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“…Arsenic is the most widely used silicon dopant for n-type layers in this context. 7,8 Here, we investigate the diffusion and segregation of ultrashallow Sb implants. 1 and 2͒.…”

Section: Introductionmentioning

confidence: 99%

Diffusion and segregation of shallow As and Sb junctions in silicon

Krüger

Rücker

Heinemann

et al. 2004

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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The diffusion and segregation of Sb and As is investigated after low-energy implantation and annealing, both rapid thermal processing and furnace annealing. We demonstrate that the absence of transient enhanced diffusion effects for Sb facilitates the fabrication of significantly shallower junctions with less dopant segregation to the surface. It is shown that Sb implantation can be used to fabricate low-resistivity ultrashallow junctions suitable for source/drain extensions in n-type metal-oxide-semiconductor field effect transistors.

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“…Solid Phase Epitaxial Regrowth (SPER) has been shown to achieve supersaturation higher than the normal Si solubility limit for some dopants. A further increase in activation above SPER can be achieved by Liquid Phase Epitaxial Regrowth (LPER), using a pulsed laser for 10~100 ns [24,25,26] to locally melt the amorphized area. This laser melt anneal enables a box-like dopant profile at far beyond the equilibrium activation level.…”

Section: Supersaturationmentioning

confidence: 99%

“…This laser melt anneal enables a box-like dopant profile at far beyond the equilibrium activation level. [25] Recent studies, however, showed that melt process and dopant activation levels achievable with LPER can be highly variable due to the very short anneal and high cool-down quenching rates, [27] indicating that a significant optimization effort may be needed to use this technique.…”

Section: Supersaturationmentioning

confidence: 99%

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

Song

Blatchford

2011

Electron. Mater. Lett.

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TX 75243, U.S.A As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.

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Merits of heat assist for melt laser annealing

Cited by 5 publications

References 16 publications

(Invited) Advanced (Millisecond) Annealing in Silicon Based Semiconductor Manufacturing

(Invited) Advanced (Millisecond) Annealing in Silicon Based Semiconductor Manufacturing

Diffusion and segregation of shallow As and Sb junctions in silicon

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

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