Memory and logic integration for System-in-a-Package

Wang, M.; Suzuki, K.; Sakai, Atsushi; Dai, Wayne Wei-Ming

doi:10.1109/icasic.2001.982696

Cited by 9 publications

(5 citation statements)

References 9 publications

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“…To successfully combine area-IO DRAM with different logic chips, an interface module is very necessary for area-IO DRAM. In the previous researches, either a general interface was not considered or the proposed interface module was not suitable for area-IO DRAM/Logic integration [1][6] [7]. So, the author designed an interface module, which will be integrated on the logic chip as a hard macro.…”

Section: B Interface With Configurable Io Widthmentioning

confidence: 98%

“…The challenge we are facing now is how to integrate different technologies together cost-effectively instead of how many transistors can be built on a single die, especially for the DRAM/Logic integration [1]. As 90nm is becoming the mainstream IC fabrication technology, DRAM processing technology and logic processing technology diverge more and more even both are CMOS technologies.…”

Section: Introductionmentioning

confidence: 99%

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Area-IO DRAM/logic integration with system-in-a-package (SiP)

Wang

Dai

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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This paper presents a cost-effective area-IO DRAM (aDRAM)/Logic integration implemented with CLC (ChipLaminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the area-IO DRAM, the bandwidth of the area-IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable IO width was also developed to make this implementation platform able to be adapted by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area-IO DRAM/Logic integration with SiP technology provides significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.

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Section: B Interface With Configurable Io Widthmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Area-IO DRAM/logic integration with system-in-a-package (SiP)

Wang

Dai

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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“…However, an important limitation of CoC is that it can only be utilized when the substrate chip has sufficient size to accommodate all other chips. To address this issue, CCLC technology was introduced in [27,28]. CCLC technology employs a thin film laminate that serves multiple functions as a package substrate, wiring resource, and decoupling capacitor for the power source.…”

Section: Introductionmentioning

confidence: 99%

Advanced Thermal Control Using Chip Cooling Laminate Chip (CCLC) with Finite Element Method for System-in-Package (SiP) Technology

et al. 2023

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This paper introduces a novel approach to address thermal management challenges in system-in-package (SiP) technology, which is a significant concern in various advanced technologies. The main objective is to assess the electrical and thermal performance of the SiP model by utilizing Chip Cooling Laminate Chip (CCLC) technology. To achieve this, we employed finite element method (FEM) analysis using COMSOL Multiphysics® and MATLAB® to compare the results of electrical and thermal SiP models with and without CCLC technology. The numerical simulations revealed that, as opposed to the traditional model, the temperature variation decreased significantly with a uniform temperature distribution when employing the CCLC technology. Additionally, the thermal conduction performance of the packaging system using CCLC demonstrated remarkable reliability and resolution with cost-effective micro-devices, particularly in micro-medicine applications. The analysis of the electrical and thermal models reported a maximum error between them of 1.15 ∘C.

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“…Technological research in microelectronics is geared toward reducing component shape and sizes for better miniaturization of assemblies. 1 Among the main technologies developed for this purpose, Chip-on-Chip (CoC) assemblies, [2][3][4] mount two chips with different functions (e.g., power and control) in a sandwich. Crucially, this technology employs polymers, which are both physically and chemically resistant even at high operating temperatures, while also having low dielectric constants (to guarantee electrical insu-lation), high breakdown voltage resistance, and dimensional stability.…”

Section: Introductionmentioning

confidence: 99%

Polyethersulfone‐epoxy terminated materials as thermosetting resins for microelectronic devices

Scamporrino¹,

Mineo²,

Scamporrino³

et al. 2009

J. Polym. Sci. A Polym. Chem.

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A totally aromatic polyether/sulfone resin (PES‐E) was synthesized and tested as an insulating glue in the construction of a Chip‐on‐Chip (CoC) device. PES‐E, essentially constituted of open‐chain macromolecules of low molecular mass (Mn of about 3000 Da) with hydroxy and/or epoxy end‐groups, has a glass transition temperature of about 150 °C and is subject to crosslinking at temperatures higher than 320 °C. A CoC device was assembled using a five‐step process by interposing a layer of PES‐E between two chips. After curing, SEM cross section images showed a homogeneous crosslinked resin layer well stuck (flick and shear tests) to both chips. The chemical structure of the chains and the hydroxy/epoxy end‐groups ratio were optimized to obtain a crosslinked material with good adhesion and sufficient flexibility to avoid cracking during assembly and use. © 2009 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 47: 5682–5689, 2009

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Memory and logic integration for System-in-a-Package

Cited by 9 publications

References 9 publications

Area-IO DRAM/logic integration with system-in-a-package (SiP)

Area-IO DRAM/logic integration with system-in-a-package (SiP)

Advanced Thermal Control Using Chip Cooling Laminate Chip (CCLC) with Finite Element Method for System-in-Package (SiP) Technology

Polyethersulfone‐epoxy terminated materials as thermosetting resins for microelectronic devices

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