Medium Frequency Physical Vapor Deposited Al₂O₃and SiO₂as Etch-Stop-Layers for Amorphous Indium-Gallium-Zinc-Oxide Thin-Film-Transistors

Abstract

In this work, we report on amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with medium frequency physical vapor deposited (mf-PVD) etch-stop-layer (ESL). TFT with mf-PVD ESL show comparable characteristics such as fieldeffect mobility (μ FE ), sub-threshold slope (SS −1 ) and current ratio (I ON/OFF ) to the conventional plasma enhanced chemical vapor deposition (PECVD) ESL based TFT, however significant differences were observed in gate bias-stress stabilities. The TFTs with mf-PVD ESL showed lower threshold-voltage (V TH ) shifts compared to TFTs with PECVD ESL when stressed under a gate field of +/−1 MV/cm for duration of 10 4 seconds in dark and light conditions. We associate the better bias-stress stability of the mf-PVD ESL based TFT to better passivating properties and the low hydrogen content of the mf-PVD layer compared to PECVD layer. Amorphous oxide semiconductors (AOSs) are gaining traction to replace the a:SiH in TFTs applied in liquid crystal display (LCD) and organic light-emitting diode display (OLED) backplanes. These oxide semiconductor have high transparency and relatively high electron mobility in the amorphous state. An additional advantage lies in the low process temperature required for AOS integration on plastic film and so potentially enabling flexible transparent display and electronics. Among many AOSs, a-IGZO is the most promising due to its high mobility, excellent uniformity, and the compatibility with transparent and flexible substrate, as compared to conventional amorphous and polycrystalline silicon.1-8 For either LCD or OLED displays with IGZO backplane, bottom-gate top-contact (BGTC) ESL configuration is preferred. The ESL protects the a-IGZO back channel from damages caused during the source-drain metallization and patterning.9-11 The damage-free surface improves the bias stabilities especially at accelerated bias stress conditions under illumination. However commonly the ESL is deposited by plasma assisted CVD processes to which a-IGZO can be sensitive.12 Therefore there is a need to investigate the effect of the ESL on the characteristics of a-IGZO TFTs.PECVD based SiO 2 deposited at temperature higher than 350• C using SiH 4 /N 2 O chemistry is commonly used as an ESL in Flat-PanelDisplay (FPD) industry due to its fast deposition rate, high uniformity and good step coverage. For the integration on commercialized flexible substrates like PEN or polyimide, deposition and process temperature should be lower to prevent shrinkage of the plastic foil and allow easy de-lamination. It is known that PECVD layer deposited at lower temperature deteriorate layer quality leading to lower density, higher amount of dangling bonds and an increase in the amount of hydrogen incorporated into the SiO 2 layer. The poor density and increase of hydrogen is problematic for a-IGZO TFTs because it leads to uncontrolled doping density. [13][14] Few research groups have demonstrated the use of PVD based dielectrics (SiO 2 and Al 2 O 3 ) as passivation layer or ESL as an altern...

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

“…Since, no significant change was observed in the gate current (I GS ), which remainedofthe order of nanoamperes, it is inferred that the interface of the BG dielectric and a-IGZO appears to remain essentially intact during the deposition of the TG dielectric. About a six-fold increase in the drain current can be attributed to the improved channel conductance caused by the emergence of defects at the Ta 2 O 5 /a-IGZO interface.Dielectric deposition in an argon plasma is reported to enhance the conductivity of both the a-IGZO films [17,24] and the source/drain regions [23]. Such behaviour was also observed in this work upon utilization of argon plasma for dielectric (Al 2 O 3 ) deposition.…”

“…However, the exposure of the a-IGZO channel to Ar plasma during deposition of the top dielectric increases the channel conductivity resulting in deteriorated TFT characteristics [17]. Therefore,TG dielectric deposition through RF sputtering in Ar plasma could affect the TFT characteristics, which has been reported to be overcome up to certain extent by using an optimum ratio of Ar/O 2 plasma to deposit Al 2 O 3 film for passivation of thea-IGZO TFT [24] and a double stack channel layer [20]. Moreover, Takechi et al [16] used aTG dielectric (Ta 2 O 5 ) deposited in Ar/O 2 plasma and reported that the sputtered dielectric films suffer from ahigher number of defects and low mass density leading to penetration of the buffer fluids in the film resulting in the higher drift rate in the sensors.…”

Impact of the Low Temperature Gate Dielectrics on Device Performance and Bias-Stress Stabilities of a-IGZO Thin-Film Transistors

“…There are many reports on the TFT stability with respect to the impact of channel layer, the environment, the passivation dielectric, and the gate dielectric. [1][2][3][4][5][6][7][8] It can be concluded from these reports that gate dielectrics characteristics contributes largely on the bias stress stabilities of the TFTs. The characteristics of gate dielectric depend upon their deposition techniques i.e.…”

Impact of source/drain contacts formation of self‐aligned amorphous‐IGZO TFTs on their negative‐bias‐illumination‐stress stabilities

“…It has been reported that high hydrogen content in a‐IGZO layer negatively impact the NBIS stabilities of the TFTs …”