The amorphous oxide semiconductor Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) has gained a large technological relevance as a semiconductor for thin‐film transistors in active‐matrix displays. Yet, major questions remain unanswered regarding the atomic origin of threshold voltage control, doping level, hysteresis, negative bias stress (NBS), and negative bias illumination stress (NBIS). We undertake a systematic study of the effects of oxygen vacancies on the properties of a‐IGZO by relating experimental observations to microscopic insights gained from first‐principle simulations. It is found that the amorphous nature of the semiconductor allows unusually large atomic relaxations. In some cases, oxygen vacancies are found to behave as perfect shallow donors without the formation of structural defects. Once structural defects are formed, their transition states can vary upon charge and discharge cycles. We associate this phenomenon to a possible presence of hysteresis in the transfer curve of the devices. Under NBS, the creation of oxygen vacancies becomes energetically very stable, hence thermodynamically very likely. This generation process is correlated with the occurrence of the negative bias stress instabilities observed in a‐IGZO transistors. While oxygen vacancies can therefore be related to NBS and hysteresis, it appears unlikely from our results that they are direct causes of NBIS, contrary to common belief.

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We suggest an analytic theory based on the effective medium approximation (EMA) which is able to describe charge-carrier transport in a disordered semiconductor with a significant degree of degeneration realized at high carrier concentrations, especially relevant in some thin-film transistors (TFTs), when the Fermi level is very close to the conduction-band edge. The EMA model is based on special averaging of the Fermi-Dirac carrier distributions using a suitably normalized cumulative density-of-state distribution that includes both delocalized states and the localized states. The principal advantage of the present model is its ability to describe universally effective drift and Hall mobility in heterogeneous materials as a function of disorder, temperature, and carrier concentration within the same theoretical formalism. It also bridges a gap between hopping and bandlike transport in an energetically heterogeneous system. The key assumption of the model is that the charge carriers move through delocalized states and that, in addition to the tail of the localized states, the disorder can give rise to spatial energy variation of the transport-band edge being described by a Gaussian distribution. It can explain a puzzling observation of activated and carrier-concentration-dependent Hall mobility in a disordered system featuring an ideal Hall effect. The present model has been successfully applied to describe experimental results on the charge transport measured in an amorphous oxide semiconductor, In-Ga-Zn-O (a-IGZO). In particular, the model reproduces well both the conventional Meyer-Neldel (MN) compensation behavior for the charge-carrier mobility and inverse-MN effect for the conductivity observed in the same a-IGZO TFT. The model was further supported by ab initio calculations revealing that the amorphization of IGZO gives rise to variation of the conduction-band edge rather than to the creation of localized states. The obtained changes agree with the one we used to describe the charge transport. We found that the band-edge variation dominates the charge transport in high-quality a-IGZO TFTs in the above-threshold voltage region, whereas the localized states need not to be invoked to account for the experimental results in this material.

The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration of relatively simple electronics, for example through ‘stick-on' electronics labels. We believe the future evolution of this technology will be governed by Wright's Law, which was first proposed in 1936 and states that the cost of a product decreases with cumulative production. This implies that a generic electronic device that can be tailored for application-specific requirements during downstream integration would be a cornerstone in the development of the Internet of Things. We present an 8-bit thin-film microprocessor with a write-once, read-many (WORM) instruction generator that can be programmed after manufacture via inkjet printing. The processor combines organic p-type and soluble oxide n-type thin-film transistors in a new flavor of the familiar complementary transistor technology with the potential to be manufactured on a very thin polyimide film, enabling low-cost flexible electronics. It operates at 6.5 V and reaches clock frequencies up to 2.1 kHz. An instruction set of 16 code lines, each line providing a 9 bit instruction, is defined by means of inkjet printing of conductive silver inks.

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O2/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.

-A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field-effect mobility of 12.0 cm 2 /(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF ) of >10 7. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (À1.0 MV/cm) bias direction after extended stressing time of 10 4 s. We achieve a stage-delay of~19.6 ns at V DD = 20 V measured in a 41-stage ring oscillator. A top-emitting quarter-quarter-video-graphics-array active-matrix organic light-emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V DD ), the brightness of the display exceeds 150 cd/m 2 .

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO2 as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μFE) of 16.0 cm2/(V.s), sub‐threshold slope (SS−1) of 0.23 V/decade and off‐currents (IOFF) < 1.0 pA. The TFTs with mf‐PVD SiO2 ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO2 ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μFE, SS−1, and IOFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/−1 MV/cm for duration of 104 s. The TFTs with mf‐PVD SiO2 ESL showed lower threshold‐voltage (VTH) shifts compared with TFTs with 300 °C PECVD SiO2 ESL and TFTs with 200 °C PECVD SiO2 ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO2 ESL TFTs to the low hydrogen content of the mf‐PVD SiO2 layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.

We investigate the relationship between charge concentration, exciton concentration, and photocurrent generation in fullerene-containing heterojunction diodes. Impedance measurements on C 60 diodes reveal a charge buildup at the C 60 /bathocuproine (BCP) interface that can be swept out under reverse bias. In solar cell structures, a similar charge buildup is observed in dark conditions, and increases as a function of incident light intensity. Photoluminescence measurements reveal that the C 60 exciton concentration is voltage dependent, explained via the process of exciton-polaron annihilation. This process has a negative impact on the generated photocurrent of the solar cells and thereby decreases the fill factor. A combination of electroabsorption, photoluminescence, and impedance measurements reveal a decrease in charge buildup and the associated exciton-polaron annihilation through the use of a BCP/3,4,9,10-perylenetetracarboxylic bis-benzimidazole/Ag cathode.