“…This fact is related to a large extent to the constant tendency to structure miniaturization (Bermejo et al, 2016;Long et al, 2016) (which correspondingly results in increasing "thermal" loads on them), as well as requires structure operation speed (Hofmann et al, 2004) In this connection much attention is being given to metal-insulator-semiconductor structures and physical-mechanical processes that are basic to their operation: solid-state reactions at interfaces (Popok et al, 2016;Dornic et al, 2018;Pichkur et al, 2015), diffusion and aggregation of complexes, generation-recombination processes of charge carriers (Woirgard et al, 2015;Brincker et al, 2018), problems of heat conduction in multilayer media (Skvortsov et.al., 2016a;Hu et, al., 2012) It is also known that a semiconductor crystal is subjected to high thermoelastic stresses in the power of electronic devices, especially under the pulsed operating conditions (Gavryushin et al, 2018a;Gavryushin et al, 2018b). In this case, the metallization systems, contacts, and near-contact areas of a semiconductor structure are the most "vulnerable", because they have many interfaces and geometrical heterogeneities (Orlov et al, 2003b;Skvortsov and Karizin, 2012;Skvortsov et al, 2016a;Ruffilli et al, 2017;). Therefore, the purpose of the present work is an investigation of the effect of thin dielectric layers on the heating dynamics of interconnections on silicon under a surface thermal shock.…”