Measurement of thermal conductivity of buried oxides of silicon-on-insulator wafers fabricated by separation by implantation of oxygen technology

He, Ping; Liu, Litian; Tian, Li; Z, Li

doi:10.1063/1.1506784

Cited by 13 publications

(6 citation statements)

References 3 publications

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“…As the temperature increases, the conductivity does not decrease significantly, which is a similar trend to that in in-plane data. [19] This implies that internal scattering is not dominant in the present temperature regime since the Umklapp scattering has 1/T dependence on temperature. [20] The ratio of the thermal conductivity of 30 nm, 17 nm, and 10 nm SOI over the bulk value is only ∼ 6.9%, ∼ 4.3%, and ∼ 3.8% at 300 K, respectively.…”

Section: Resultsmentioning

confidence: 80%

Thermal conductivity characterization of ultra-thin silicon film using the ultra-fast transient hot strip method*

Zhang¹,

Cheng²,

Ni³

et al. 2019

Chinese Phys. B

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Thermal conductivity is an important material parameter of silicon when studying the performance and reliability of devices or for guiding circuit design when considering heat dissipation, especially when the self-heating effect becomes prominent in ultra-scaled MOSFETs. The cross-plane thermal conductivity of a thin silicon film is lacking due to the difficulty in sensing high thermal conductivity in the vertical direction. In this paper, a feasible method that utilizes an ultra-fast electrical pulse within 20 μ s combined with the hot strip technique is adopted. To the best of our knowledge, this is the first work that shows how to extract the cross-plane thermal conductivity of sub-50 nm (30 nm, 17 nm, and 10 nm) silicon films on buried oxide. The ratio of the extracted cross-plane thermal conductivity of the silicon films over the bulk value is only about 6.9%, 4.3%, and 3.8% at 300 K, respectively. As the thickness of the films is smaller than the phonon mean free path, the classical heat transport theory fails to predict the heat dissipation in nanoscale transistors. Thus, in this study, a ballistic model, derived from the heat transport equation based on extended-irreversible-hydrodynamics (EIT), is used for further investigation, and the simulation results exhibit good consistence with the experimental data. The extracted effective thermal data could provide a good reference for precise device simulations and thermoelectric applications.

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Section: Resultsmentioning

confidence: 80%

Thermal conductivity characterization of ultra-thin silicon film using the ultra-fast transient hot strip method*

Zhang¹,

Cheng²,

Ni³

et al. 2019

Chinese Phys. B

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“…The electrical conductivity of the TiN filaments is calculated from our measured data. The parameters for Si and SiO2 come from references [26][27][28]. It can be seen that even at high annealing temperatures, the temperature drops to less than 100°C within a few micrometres of the device under test, and so nearby devices remain unaffected.…”

Section: Electrically Annealing For DC and Mzimentioning

confidence: 99%

Electrically Erasable Optical I/O for Wafer Scale Testing of Silicon Photonic Integrated Circuits

Chen

Milošević

et al. 2020

IEEE Photonics J.

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A technique for realizing electrically erasable photonics devices using micro-heaters for localized annealing of lattice defects in silicon is presented. The lattice defects have previously been introduced by ion implantation in order to cause a refractive index change. This technique can be used to fabricate electrically erasable on-chip directional couplers (DCs) and Mach-Zehnder Interferometer (MZI) switches. These devices can be used for wafer scale testing of photonics circuits, allowing testing of individual optical components in a complex photonic integrated circuit, or components for programmable optical circuits, whilst inducing negligible additional optical loss when erased electrically. In this paper, we report the designs and experimental results of fully, rapidly annealing of these devices.

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“…An isothermal (I-T) 300 K heat sink is placed at the bottom of the underlying 1.8μm-thick Si layer, and at the top of the 200 nm-thick SiO 2 passivation layer; S/D electrodes are set as I-T 300 K BC, and a lumped thermal resistance R th =2 * 10 −4 cm 2 K/W is connected between the gate and an ideal 300 K heat sink. This lumped resistance takes into account the thermal resistance due to the gate dielectric and to the gate-SiO 2 interface [10]. Finally, the vertical x−y and z−y planes (see Fig.…”

Section: Simulation Approachmentioning

confidence: 99%

Simulation of self-heating effects in 30nm gate length FinFET

Braccioli

Curatola

Yang

et al. 2008

2008 9th International Conference on Ultimate Integration of Silicon

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Measurement of thermal conductivity of buried oxides of silicon-on-insulator wafers fabricated by separation by implantation of oxygen technology

Abstract: Articles you may be interested inMechanisms of positive charge generation in buried oxide of UNIBOND and separation by implanted oxygen silicon-on-insulator structures during high-field electron injection

Cited by 13 publications

References 3 publications

Thermal conductivity characterization of ultra-thin silicon film using the ultra-fast transient hot strip method*

Thermal conductivity characterization of ultra-thin silicon film using the ultra-fast transient hot strip method*

Electrically Erasable Optical I/O for Wafer Scale Testing of Silicon Photonic Integrated Circuits

Simulation of self-heating effects in 30nm gate length FinFET

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