Maximum and Maximal Weight Matching Dispatching Schemes for MSM Clos-Network Packet Switches

Rojas‐Cessa, Roberto; Oki, Eiji; Chao, H. Jonathan

doi:10.1587/transcom.e93.b.297

Cited by 6 publications

(3 citation statements)

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“…The first is a ''request-grant-accept'' iterative matching process between virtual output queues (VOQs) and the output ports of IMs, and the second is a ''request-grant'' iterative matching process between IMs and CMs. And [14] proposed maximum and maximal weight matching dispatching schemes for MSM CLOS-Networks. These two dispatching schemes are also inter-stage scheduling algorithms, and they use iterative weight-based matching algorithms, which are based on the oldest-cell-first (OCF) selection.…”

Section: B Scheduling Algorithmsmentioning

confidence: 99%

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Design of a 640-Gbps Two-Stage Switch Fabric for Satellite On-Board Switches

Qiao

Chen

2020

IEEE Access

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Due to the limitation of hardware resources and high reliability requirements for satellite-borne switching equipments and the demand for the increasing network bandwidth, a new type of two-stage satellite on-board switch fabric is presented in this paper. The fully connected structure is composed of eight input modules and eight output modules. And each module has four shared-buffer memories, which guarantee the premise of high-throughput. Compared with the traditional three-stage CLOS switch fabric, central modules are not used in this design. And compared with the complicated inter-stage scheduling algorithm, this paper uses an improved WRR algorithm which supports multi-priority variable-length packets scheduling. This design reduces the consumption of hardware resources and meets the design requirements of satellite-borne switches. In addition, we used the Xilinx FPGA to implement this 32 × 32 two-stage switch fabric, and used ModelSim 10.6d to simulate and analyze the entire design. The simulation results show that the peak throughput of this structure can reach 640 Gbps when the system clock frequency is 200 MHz.INDEX TERMS Satellite on-board switch, high-throughput, two-stage, shared-buffer memory, FPGA. I. INTRODUCTIONSatellite communication technology has developed rapidly and achieved great success in recent years. Compared with terrestrial communication network, satellite communication network has the advantages of wide coverage, less affected by geographical environment factors, larger bandwidth, and cost independent of communication distance, etc [1]. Satellite communication network is an important part of the next generation Internet, and it is also one of the research hotspots in the field of science and technology.In the information era, Internet has penetrated into all walks of life, and it has become an indispensable part of people's work, life and production. At present, people's demand for network bandwidth has far exceeded the existing network switching capacity, which brings severe challenges to the current satellite network. As the key device of the network node, the performance of switch will directly affect the network delay, throughput and other important parameters [2]. Therefore, it is of great significance to study the highthroughput satellite-borne switch for satellite network.

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Section: B Scheduling Algorithmsmentioning

confidence: 99%

“…In Section II, we introduced some scheduling algorithms. These intra-stage [12] and inter-stage [13], [14], [18] scheduling algorithms have high throughput by using multiple iterative matches, but they are complex and require longer arbitration time.…”

Section: Design and Improvement Of Scheduling Algorithms A Scheduling...mentioning

confidence: 99%

Design of a 640-Gbps Two-Stage Switch Fabric for Satellite On-Board Switches

Qiao

Chen

2020

IEEE Access

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“…Most of the packet dispatching schemes developed for the three-stage Clos-network switches insist on using the request-grant-accept handshaking routine, based on the effect of the desynchronization of arbitration pointers [9,10]. In this routine, if cells are waiting for transmission in queues, input arbiters send requests to corresponding output port arbiters.…”

Section: Related Work and Motivationmentioning

confidence: 99%

Packet dispatching using module matching in the modified MSM Clos-network switch

Kleban

2017

Telecommun Syst

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A modified memory-space-memory (MSM) Closnetwork switch, called MCNS, with a module-level matching packet dispatching scheme, is presented in the paper. The MCNS is a modification of the MSM Clos-network switch proposed to simplify the packet dispatching scheme. In this paper, we evaluate the combinatorial properties of the MCNS, as well as a new module-level matching packet dispatching algorithm. We also show how this algorithm can be implemented in an field-programmable gate array chip. Selected simulation results obtained for the MCNS are compared with the results obtained for the MSM Clos-network switch using other module-level matching algorithms.

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Module-level matching algorithms for MSM clos-network switches

Xia

Chao

2012

2012 IEEE 13th International Conference on High Performance Switching and Routing

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Maximum and Maximal Weight Matching Dispatching Schemes for MSM Clos-Network Packet Switches

Cited by 6 publications

References 19 publications

Design of a 640-Gbps Two-Stage Switch Fabric for Satellite On-Board Switches

Design of a 640-Gbps Two-Stage Switch Fabric for Satellite On-Board Switches

Packet dispatching using module matching in the modified MSM Clos-network switch

Module-level matching algorithms for MSM clos-network switches

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