Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

Popp, Thomas; Mangard, Stefan

doi:10.1007/11545262_13

Cited by 288 publications

(164 citation statements)

References 15 publications

(19 reference statements)

Supporting

Mentioning

163

Contrasting

Unclassified

Order By: Relevance

“…As one of the recent research, Masked Dual-Rail Pre-Charge Logic (MDPL) [9] that improved WDDL was proposed at CHES 2005 conference. The proposers of MDPL claim that it can implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route because the difference of loading capacitance between all pairs of complementary logic gates in MDPL can be covered up by the random masking.…”

Section: Introductionmentioning

confidence: 99%

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Suzuki

Saeki

2006

Lecture Notes in Computer Science

112

View full text Add to dashboard Cite

Abstract. In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new countermeasure named Masked Dual-Rail Pre-Charge Logic (MDPL) which combine dual-rail circuits with random masking to improve Wave Dynamic Differential Logic (WDDL). The proposers of MDPL claim that it can implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route because the difference of loading capacitance between all pairs of complementary logic gates in MDPL can be covered up by the random masking. In this paper, we especially focus the signal transition of the MDPL gate and evaluate the DPA-resistance of MDPL in detail. Our evaluation results show that the leakage occurs in the MDPL gates as well as WDDL gates when input signals have difference of delay time even if MDPL has an effectiveness on reducing the leakage caused by the difference of loading capacitance. Furthermore, we demonstrate the problem with different input signal delays by measurements of an FPGA and show the validity of our evaluation.

show abstract

Section: Introductionmentioning

confidence: 99%

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Suzuki

Saeki

2006

Lecture Notes in Computer Science

112

View full text Add to dashboard Cite

show abstract

“…in [9], or the combination of both, e.g. in [17] have been proposed as solutions to increase to security of an implementation against side-channel adversaries. Although side-channel attacks have been intensively investigated in the recent years [6], the fair evaluation of these different countermeasures has been a long standing open question.…”

Section: Introductionmentioning

confidence: 99%

Information Theoretic Evaluation of Side-Channel Resistant Logic Styles

Macé

Standaert

Quisquater

Cryptographic Hardware and Embedded Systems - CHES 2007

View full text Add to dashboard Cite

Abstract. We propose to apply an information theoretic metric to the evaluation of side-channel resistant logic styles. Due to the long design and development time required for the physical evaluation of such hardware countermeasures, our analysis is based on simulations. Although they do not aim to replace the need of actual measurements, we show that simulations can be used as a meaningful first step in the validation chain of a cryptographic product. For illustration purposes, we apply our methodology to gate-level simulations of different logic styles and stress that it allows a significant improvement of the previously considered evaluation methods. In particular, our results allow putting forward the respective strengths and weaknesses of actual countermeasures and determining to which extent they can practically lead to secure implementations (with respect to a noise parameter), if adversaries were provided with simulation-based side-channel traces. Most importantly, the proposed methodology can be straightforwardly adapted to adversaries provided with any other kind of leakage traces (including physical ones).

show abstract

“…At cell level, the most relevant proposals are Random Switching Logic (RSL) [4], Dual Random Switching Logic (DRSL) 30 2 [5] and Masked Dual-Rail Precharge Logic (MDPL) [6]. Moreover, it has been shown that in general the security of cell level implementations could be compromised due to the effect of the inter-wire capaci-45 tances [7] or the so-called early propagation effect [8] [9].…”

Section: Introductionmentioning

confidence: 99%

A new countermeasure against side-channel attacks based on hardware-software co-design

Lumbiarres-Lopez

López-García

Canto-Navarro

2016

Microprocessors and Microsystems

View full text Add to dashboard Cite

This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software codesign. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key.

show abstract

Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

Cited by 288 publications

References 15 publications

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Information Theoretic Evaluation of Side-Channel Resistant Logic Styles

A new countermeasure against side-channel attacks based on hardware-software co-design

Contact Info

Product

Resources

About