Information Theoretic Evaluation of Side-Channel Resistant Logic Styles

Macé, François; Standaert, François‐Xavier; Quisquater, Jean-Jacques

doi:10.1007/978-3-540-74735-2_29

Cited by 50 publications

(40 citation statements)

References 19 publications

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“…That is, we use idealized leakage functions in order to illustrate interesting features of our model. Applications to more complex and practically meaningful contexts can be found in other publications [24,34,36,35].…”

Section: Applications Of the Modelmentioning

confidence: 99%

A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks

Standaert

Malkin

Yung

2009

Lecture Notes in Computer Science

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672

557

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Abstract. The fair evaluation and comparison of side-channel attacks and countermeasures has been a long standing open question, limiting further developments in the field. Motivated by this challenge, this work makes a step in this direction and proposes a framework for the analysis of cryptographic implementations that includes a theoretical model and an application methodology. The model is based on commonly accepted hypotheses about side-channels that computations give rise to. It allows quantifying the effect of practically relevant leakage functions with a combination of information theoretic and security metrics, measuring the quality of an implementation and the strength of an adversary, respectively. From a theoretical point of view, we demonstrate formal connections between these metrics and discuss their intuitive meaning. From a practical point of view, the model implies a unified methodology for the analysis of side-channel key recovery attacks. The proposed solution allows getting rid of most of the subjective parameters that were limiting previous specialized and often ad hoc approaches in the evaluation of physically observable devices. It typically determines the extent to which basic (but practically essential) questions such as "How to compare two implementations? " or "How to compare two side-channel adversaries? " can be answered in a sound fashion.

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Section: Applications Of the Modelmentioning

confidence: 99%

A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks

Standaert

Malkin

Yung

2009

Lecture Notes in Computer Science

Self Cite

672

557

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“…SABL [35]). Again, there is a security vs. performance tradeoff since designing full-custom hardware is more expensive (at least in development time) than using standard libraries, but the security of the latter ones is generally lower, mainly because they offer less fine tuning possibilities [16].…”

Section: Related Workmentioning

confidence: 99%

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices

Medwed

Standaert

Großschädl

et al. 2010

Lecture Notes in Computer Science

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101

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The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-preserving applications. In this context, RFID tags need to be protected against physical attacks such as Differential Power Analysis (DPA) and fault attacks. The main obstacles towards secure RFID are the extreme constraints of passive tags in terms of power consumption and silicon area, which makes the integration of countermeasures against physical attacks even more difficult than for other types of embedded systems. In this paper we propose a fresh re-keying scheme that is especially suited for challenge-response protocols such as used to authenticate tags. We evaluate the resistance of our scheme against fault and side-channel analysis, and introduce a simple architecture for VLSI implementation on RFID tags. In addition, we estimate the cost of our scheme in terms of area and execution time for various sec... Abstract. The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-preserving applications. In this context, RFID tags need to be protected against physical attacks such as Differential Power Analysis (DPA) and fault attacks. The main obstacles towards secure RFID are the extreme constraints of passive tags in terms of power consumption and silicon area, which makes the integration of countermeasures against physical attacks even more difficult than for other types of embedded systems. In this paper we propose a fresh re-keying scheme that is especially suited for challenge-response protocols such as used to authenticate tags. We evaluate the resistance of our scheme against fault and side-channel analysis, and introduce a simple architecture for VLSI implementation on RFID tags. In addition, we estimate the cost of our scheme in terms of area and execution time for various security/performance trade-offs. Our experimental results show that the proposed re-keying scheme provides better security (and does so at less cost) than other state-of-the-art countermeasures.

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“…To evaluate and fairly compare the side-channel leakage of our target designs we applied the information theoretic (IT) analysis of [29] as it has been used for the same purpose e.g., in [16]. So, we collected 512, 000 traces for each target design, i.e., 2000 traces for each S-box input value.…”

Section: Practical Investigationsmentioning

confidence: 99%

“…-The AES S-box circuit operates in precharge-evaluation mode, and in contrast to a CMOS combinatorial circuit its leakage does not depend on two consecutive inputs (input transitions). Therefore, our selection of estimating the probabilities based on the S-box input is a valid choice (the same is given in [16]). …”

Section: Practical Investigationsmentioning

confidence: 99%

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs

Moradi

Immler

2014

Advanced Information Systems Engineering

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Abstract. This work deals with DPA-resistant logic styles, i.e., celllevel countermeasures against power analysis attacks that are known as a serious threat to cryptographic devices. Early propagation and imbalanced routings are amongst the well-known issues of such countermeasures, that -if not considered during the design process -can cause the underlying cryptographic device to be vulnerable to certain attacks. Although most of the DPA-resistant logic styles target an ASIC design process, there are a few attempts to apply them in an FPGA platform. This is due to the missing freedom in FPGA design tools required to deal with the aforementioned problems. Our contribution in this work is to provide solutions for both early propagation and imbalanced routings considering a modern Xilinx FPGA as the target platform. Foremost, based on the WDDL concept we design a new FPGA-based logic style without early propagation in both precharge and evaluation phases. Additionally, with respect to the limited routing resources within an FPGA we develop a customized router to find the best appropriate dual-rail routes for a given dual-rail circuit. Based on practical experiments on a Virtex-5 FPGA our evaluations verify the efficiency of each of our proposed approaches. They significantly improve the resistance of the design compared to cases not benefiting from our schemes.

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Information Theoretic Evaluation of Side-Channel Resistant Logic Styles

Cited by 50 publications

References 19 publications

A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks

A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs

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