Abstract-This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using three statistical methods which are based on correlation, the Welch's t-test and the difference of means.Index Terms-Security, side-channel attacks, power analysis attacks, softwarehardware countermeasuresTHE addition of countermeasures for protecting the key in cryptographic algorithms has become an emerging field of research, since in the late 1990s several authors revealed the inherent weakness associated with physical devices used in their implementation [1]. When a cryptographic algorithm is implemented in a hardware device, it could be shown as both its power consumption and its electromagnetic radiation (EM) are heavily dependent on the data that are being processed. Since data rely on the cryptographic key, this dependence can be exploited to find out such a key by using a statistical method of analysis. Further, as the leakage information that is exploited is external to the hardware device, these methods are usually known as Side-Channel Analysis (SCA) attacks.The most widely used statistical method is based on the calculation of the correlation between the captured power trace (or the EM) and a theoretical model of power consumption for a specific key. In order to obtain such a model, it is necessary to know both the data that are being processed and the behaviour of the basic CMOS cells that form the circuit. This model is usually approximated by the Hamming distance (HD) or the Hamming weight (HW) related to the binary value of the particular point to be attacked in the circuit [2]. This approximation is based on the assumption that the actual consumption is proportional to HW or HD. The former represents the number of ones included in a byte vðt k Þ at instant t k , whereas the latter is based on the HW of the result obtained when operating with an exclusive-OR the value of byte v at instants t kÀ1 and t k (i.e., vðt kÀ1 Þ and vðt k Þ). Nevertheless, the knowledge of data is more complicated, since such data depend not only on the plain text to be encrypted but also on the value of the cryptographic key. Generally, it ...
This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software codesign. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key.
This paper presents a new proposal for hiding the cryptographic key, when the so-called side-channel attacks (SCAs) are applied to break the security of AES-128. The algorithm was executed on MicroBlaze, but the proposed method is generic and can be extended to any other microprocessor. SCAs are based on examining the correlation produced between the data and operations performed by the microprocessor and its actual power consumption. Traditionally, such weakness is counteracted by introducing countermeasures addressed to reduce as much as possible this correlation, making data and power consumption independent. On the contrary, the proposal presented in this paper introduces some modifications in the AES algorithm. These changes aim at concealing the true key by reinforcing the correlation coefficient in such a way that a classical attack leads to a false key. This way, the system misleads the attacker and apparently behaves as an unprotected system that, in fact, reveals a false positive. The complete system was built on a Virtex-5 FPGA. Experimental results show the strength of our implementation, which is capable of successfully hiding the true cryptographic key.Postprint (published version
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