MaPU: A novel mathematical computing architecture

Wang, Donglin; Du, Xiaoyong; Yin, Leizu; Lin, Cong; Ma, Hong; Ren, Weili; Wang, Huijuan; Wang, Xingang; Xie, Shijie; Wang, Lei; Liu, Zijun; Wang, Tao; Pu, Zhonghua; Ding, Guangxin; Zhu, Mengchen; Yang, Liang; Guo, Ruoshan; Zhang, Zhiwei; Lin, Xiao; Hao, Jie; Yang, Y. S.; Sun, Wenqin; Zhou, Fabiao; Xiao, NuoZhou; Cui, Qian; Wang, Xiaoqin

doi:10.1109/hpca.2016.7446086

Cited by 15 publications

(11 citation statements)

References 19 publications

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“…Compared with Shih's approach [6], we obtain 17.2% decrement on skew result while we also use 24.5% less capacitance resource on the average, with only about 17% runtime overhead. Additionally, we have applied our symmetrical CTS algorithm into the MaPU core physical design [1]. The MaPU cores in this chip are called APE, which stands for Algebraic Processing Engine.…”

Section: Resultsmentioning

confidence: 99%

“…We test our proposed algorithm on both public benchmarks [3,8] and one ASIC physical design [1]. By using our algorithm flow, the level number, skew results and capacitance cost are all reduced.…”

Section: Introductionmentioning

confidence: 99%

“…Related papers [1,2] indicate that clock network typically contributes more than 40% of the entire chip power. On the other hand, as the technology of semiconductor process is scaling down to 10 nm and below, clock tree synthesis becomes even more challenging due to on-chip variation (OCV) effects [3].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis

Liu

Zhang

Sun

et al. 2017

IEICE Electron. Express

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Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis

Liu

Zhang

Sun

et al. 2017

IEICE Electron. Express

Self Cite

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“…This can be achieved using domain-specific hardware accelerators [1]. Besides employing architectural solutions, it is critical for a compiler to reduce the execution time of applications by taking into account the architectural features of the hardware platform [17].…”

Section: Introductionmentioning

confidence: 99%

“…There have been various efforts to design vision-processing systems targeting CV applications such as [2,[17][18][19], among others. One such effort is Myriad 2 platform from Movidius [20].…”

Section: Introductionmentioning

confidence: 99%

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Mustafa

O’Riordan

Rogers

et al. 2018

J Real-Time Image Proc

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Computer vision applications are becoming more and more popular in embedded systems such as drones, robots, tablets, and mobile devices. These applications are both compute and memory intensive, with memory bound stalls (MBS) making a significant part of their execution time. For maximum reduction in memory stalls, compilers need to consider architectural details of a platform and utilize its hardware components efficiently. In this paper, we propose a compiler optimization for a vision-processing system through classification of memory references to reduce MBS. As the proposed optimization is based on the architectural features of a specific platform, i.e., Myriad 2, it can only be applied to other platforms having similar architectural features. The optimization consists of two steps: affinity analysis and affinity-aware instruction scheduling. We suggest two different approaches for affinity analysis, i.e., source code annotation and automated analysis. We use LLVM compiler infrastructure for implementation of the proposed optimization. Application of annotation-based approach on a memory-intensive program shows a reduction in stall cycles by 67.44%, leading to 25.61% improvement in execution time. We use 11 different image-processing benchmarks for evaluation of automated analysis approach. Experimental results show that classification of memory references reduces stall cycles, on average, by 69.83%. As all benchmarks are both compute and memory intensive, we achieve improvement in execution time by up to 30%, with a modest average of 5.79%.

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