A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis

Abstract

Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.

Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

“…Therefore, we can set weight values for different emphasis requirements, and the physical layout process also verifies the feasibility of the proposed methodology. In order to further verify the effectiveness of the design method applied to the physical layout (IP modules that have been taped) [28][29][30], we conducted an experimental comparison with a commercial EDA tool flow, where the commercial EDA tool flow is a fully automatic clock tree synthesis method. Based on the proposed clock mesh design method, we optimized the experimental results through a fine-tuning hierarchical clock network.…”

Progress in a novel architecture for high performance processing

“…Additionally, we have developed a third-party EDA tool for the clock network design. [28][29][30][31][32] By using this tool, the power consumption from clock network can be largely reduced, because we have found that power cost can be up to more that 40% in last version. In sum, we have optimized the new HPP processor in many aspects.…”