Clock Mesh Synthesis Methodology Based on Combinatorial Optimization

Abstract

In light of advancing technology, the conventional clock network architecture has become inadequate for addressing the intricacies inherent in modern System-on-Chip (SoC) designs. While clock mesh topology offers resilience against On-Chip Variation (OCV) fluctuations, it still necessitates manual intervention. Therefore, substantial scope exists for methodological enhancements and the refinement of rapid analytical techniques. This paper introduces a novel clock mesh synthesis approach, underpinned by dynamic programming algorithms, that guarantees latency constraints. Our experimental findings demonstrate that our algorithm achieves an additional 26.6% reduction in power consumption compared to the baseline methodology. Furthermore, it substantially reduces runtime by an average of 78.0% when contrasted with traditional simulation methods. These results highlight the potential of our methodology for enhancing the efficiency and power management of clock mesh.