Majority‐based evolution state assignment algorithm for area and power optimisation of sequential circuits

El‐Maleh, Aiman H.

doi:10.1049/iet-cdt.2015.0038

Cited by 18 publications

(27 citation statements)

References 24 publications

(52 reference statements)

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“…In this study, a binary state encoding is used, and next state function is partially included in matching. However, evolutionary state encoding algorithms such as [23] or [24] can be used to reduce the increased LUT requirement.…”

Section: Experimental Evaluationmentioning

confidence: 99%

“…The experimental results from [22][23][24] show that the evolutionary state encoding algorithms such as [23] or [24] outperform the binary or random state encoding techniques by an average of 59.72% and 64.06%, respectively. Therefore, the LUT requirement for the proposed architecture can be further reduced by 20 to 30% by using the evolutionary state encoding techniques.…”

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confidence: 99%

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FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Das

Priya

2018

International Journal of Reconfigurable Computing

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The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

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Section: Experimental Evaluationmentioning

confidence: 99%

mentioning

confidence: 99%

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Das

Priya

2018

International Journal of Reconfigurable Computing

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“…A power-optimised state encoding has been obtained for lion9 benchmark circuit using the majority-based evolution (MBE) state encoding technique [14] and has resulted in the following state encodings which requires four FFs (F 3 , F 2 , F 1 , F 0 ): {st0 = 0111, st1 = 1111, st2 = 0110, st3 = 0100, st4 = 0101, st5 = 1011, st6 = 0010, st7 = 0000 and st8 = 0001}. The generated two-level equations for the synthesised circuit are given below which has a cost of 45 literals…”

Section: Proposed Fault Tolerance State Encoding Algorithmmentioning

confidence: 99%

“…It is well known that state assignment has a strong impact on the area and power of synthesised sequential circuits [14]. While the technique in [13] derives state codes that satisfy the desired HD constraints, it does not take into consideration the optimisation of area and power of synthesised sequential circuits.…”

Section: Introductionmentioning

confidence: 99%

Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits

El‐Maleh

2017

IET Computers & Digital Techniques

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Recently, a finite state machine-based fault tolerance technique for sequential circuits based on protecting few states with high probability of occurrence has been proposed. In this study, the authors propose an algorithm that starts with a given state assignment targeting the optimisation of either area or power and generates a state assignment that preserves the original state assignment and satisfies the fault tolerance requirements for the protected states. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesised sequential circuits while enhancing their fault tolerance.

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“…The problem of state assignment can be considered in terms of integer linear programming [10], but heuristic methods are generally used [13], [14]. Genetic algorithms are sometimes applied in the process of coding [15], [16]. The search for more efficient implementations of automatons is sometimes carried out also in the form of a globally asynchronous locally synchronous (GALS) [17] structure, or solutions exploiting clock gating [18], [19].…”

Section: Introductionmentioning

confidence: 99%

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

2019

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A logic synthesis for finite-state machines (FSMs) aimed at programmable array logic (PAL)-based complex programmable logic devices is proposed here. This approach consists of the simultaneous synthesis of a transition function and an output function. The main contribution is the novel multilevel optimization of an FSM. In this process, a new form of graph is used, i.e., a graph of excitations and outputs. This is a generalization of the graph of outputs that has previously been used in the process of technology mapping of multi-output functions in PAL-based programmable structures. The main idea, the theoretical background, and a precise algorithm are illustrated by means of simple examples. The proposed algorithm was compared with other approaches by synthesizing the FSM benchmarks and mapping the solutions to k-term PAL-based logic blocks. The obtained results are compared on the basis of the area (number of logic blocks) and speed (number of logic levels). The proposed approach is especially effective for larger FSMs. INDEX TERMS CPLD, FSM, multi-level optimization, technology mapping.

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Majority‐based evolution state assignment algorithm for area and power optimisation of sequential circuits

Cited by 18 publications

References 24 publications

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

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