A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

Kubica, Marcin; Kania, Dariusz; Kulisz, Józef

doi:10.1109/access.2019.2895206

Cited by 24 publications

(34 citation statements)

References 32 publications

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“…In (24) and (25), the superscript j means that the corresponding function is generated by the Blockj. If J ≤ S L , then there is only a single level of LUTs in the circuit of BlockOR.…”

Section: Main Idea Of the Proposed Methodsmentioning

confidence: 99%

“…A table TZV j is a base to derive the SBFs (24) and (25). The terms of corresponding SOPs are conjunctions A m • X h , where A m is a conjunction of variables T r ∈ T j .…”

Section: Main Idea Of the Proposed Methodsmentioning

confidence: 99%

“…All other state variables are treated as insignificant. The SBF (24) and (25) are used to implement circuits of Block1-BlockJ.…”

Section: Main Idea Of the Proposed Methodsmentioning

confidence: 99%

“…To implement a LUT-based FSM circuit, it is necessary to execute the step of technology mapping [24][25][26][27]. The technology mapping is a very important stage of the FPGA-based design process [28].…”

Section: Introductionmentioning

confidence: 99%

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Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

et al. 2020

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Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count.

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“…In (24) and (25), the superscript j means that the corresponding function is generated by the Blockj. If J ≤ S L , then there is only a single level of LUTs in the circuit of BlockOR.…”

Section: Main Idea Of the Proposed Methodsmentioning

confidence: 99%

“…A table TZV j is a base to derive the SBFs (24) and (25). The terms of corresponding SOPs are conjunctions A m • X h , where A m is a conjunction of variables T r ∈ T j .…”

Section: Main Idea Of the Proposed Methodsmentioning

confidence: 99%

“…All other state variables are treated as insignificant. The SBF (24) and (25) are used to implement circuits of Block1-BlockJ.…”

Section: Main Idea Of the Proposed Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

et al. 2020

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“…One of the most crucial steps in the LUT-based design flow is the technology mapping [19][20][21][22][23][24][25]. During this step, an FSM circuit is converted into a network of interconnected LUTs.…”

Section: Introductionmentioning

confidence: 99%

Reducing LUT Count for FPGA-Based Mealy FSMs

2020

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Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.

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