Reducing LUT Count for FPGA-Based Mealy FSMs

Barkalov, Alexander; Titarenko, Larysa; Krzywicki, Kazimierz

doi:10.3390/app10155115

Cited by 10 publications

(65 citation statements)

References 48 publications

(99 reference statements)

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“…We do not show the characteristics of these benchmarks in this article. They can be found, for example, in [30].…”

Section: Resultsmentioning

confidence: 99%

“…Additionally, it produces FSM circuits having regular system of interconnections, where each level of logic has its unique systems of inputs and outputs. The proposed method allows obtaining FSM circuits that have slightly more LUTs and a higher operating frequency than their three-level counterparts [30]. The experimental results presented in the article show that the advantage of the proposed approach increases as the number of FSM inputs increases.…”

Section: Introductionmentioning

confidence: 93%

“…To generate functions (13), an additional block of logic should be used. In the work [30], two known methods of structural decomposition are used for reducing LUT count for FPGA-based Mealy FSMs. It results in Mealy FSM U 2 shown in Figure 3.…”

Section: State-of-the-artmentioning

confidence: 99%

“…(14) Blockλ implements the system (12) dependent on additional variables z r ∈ Z. As our investigations [30] show, this approach allows significantly reducing the LUT count as compared to equivalent FSM U 1 . However, this solution has a serious drawback: the performance of FSM U 2 is always less than it is for an equivalent Mealy FSM U 1 .…”

Section: State-of-the-artmentioning

confidence: 99%

“…The corresponding circuit includes four LUTs. The Block2 is represented by the SBF (30). Its circuit also includes four LUTs.…”

Section: Example Of Synthesismentioning

confidence: 99%

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Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

et al. 2020

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Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count.

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“…We do not show the characteristics of these benchmarks in this article. They can be found, for example, in [30].…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 93%

Section: State-of-the-artmentioning

confidence: 99%

Section: State-of-the-artmentioning

confidence: 99%

“…The corresponding circuit includes four LUTs. The Block2 is represented by the SBF (30). Its circuit also includes four LUTs.…”

Section: Example Of Synthesismentioning

confidence: 99%

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Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

et al. 2020

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FPGA Based Approximate Digital VLSI Circuit Validating Focused on Fault Diagnosis

Uthayakumar¹,

Jijina

Suresh³

et al. 2021

J. Phys.: Conf. Ser.

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In this report, a Duty Approximate Testing framework is introduced that generates modulation schemes for only separate faults. The fundamental idea is to draw up a list of flaws that may be overlooked or left unproven. The current issues are tested by generating modulation schemes for certain flaws. We examine the implications of skipping any faults by adding glued errors at the circuit’s proper position. With a system limitation standard, the output standard deviation is calculated. In the near past, the FPGA method was a leading method of addressing dynamic automated system architecture or systems. Multiple timers operate the devices in all full-duplex modes. This report examines responsibility to fix multipurpose structures on FPGA for just a grid of dynamic and partially located coordinated balanced regular intervals. For both the FPGA, throughout the irregular clock operation model, the modular component reconstruction system’s load balancing based on the remote monitoring method is used.Furthermore, DPR uses the open-goal approach’s proposed technique to eliminate the flaws throughout processing in the presence of damages. The DPR cuts the lifespan, and device storage is saved by limited restructuring in concurrent FPGA computing. The power consumption of the development method is very significant for many clock realms and throughout the grid. The balanced development consistency is compared with the concurrent balanced matrix to measure the DPR’s reliability. It is also noted that even the fault-tolerant DPR for FPGAs is highly efficient and reliable. The experimental finding shows that irrespective of the flawed findings obtained, such electronics can be used in some kinds of fault structures such as video editing, image recognition, and digital communication. The number of fault positions is reduced by 15-25% concerning both of those benefit, leading to a decline in the number of switching devices.

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Improving Hardware in LUT-Based Mealy FSMs

2022

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The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs.

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Reducing LUT Count for FPGA-Based Mealy FSMs

Cited by 10 publications

References 48 publications

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

FPGA Based Approximate Digital VLSI Circuit Validating Focused on Fault Diagnosis

Improving Hardware in LUT-Based Mealy FSMs

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