Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits

El‐Maleh, Aiman H.

doi:10.1049/iet-cdt.2016.0085

Cited by 9 publications

(6 citation statements)

References 15 publications

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“…The chip area is determined by the number of LUTs and their interconnections. As noted in [92], the deterministic algorithms "are far from being optimal".…”

Section: Saving Power By State Assignmentmentioning

confidence: 99%

“…Also, approaches such as binary particle swarm and cuckoo search are used for optimizing the static power consumption (the circuit area) [130,131]. In [92], a probabilistic swap search state assignment algorithm is proposed. It is based on (1) assigning probabilities of each pair of code swaps and (2) probabilistically exploring pairwise code swaps.…”

Section: Saving Power By State Assignmentmentioning

confidence: 99%

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Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Barkalov,

Titarenko,

Bieganowski

et al. 2024

Applied Sciences

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Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

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“…The chip area is determined by the number of LUTs and their interconnections. As noted in [92], the deterministic algorithms "are far from being optimal".…”

Section: Saving Power By State Assignmentmentioning

confidence: 99%

Section: Saving Power By State Assignmentmentioning

confidence: 99%

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Barkalov,

Titarenko,

Bieganowski

et al. 2024

Applied Sciences

View full text Add to dashboard Cite

show abstract

“…The finite state machine (FSM) is a mathematical model, which is usually used to describe the running process of a control system [34,35]. There are four basic components in a traditional basic FSM: state, transition, action, and event [36,37].…”

Section: Finite State Machine and Definition Of Signalsmentioning

confidence: 99%

Real-Time Fault Diagnosis and Fault-Tolerant Control Strategy for Hall Sensors in Permanent Magnet Brushless DC Motor Drives

et al. 2021

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The Hall sensor is the most commonly used position sensor of the permanent magnet brushless direct current (PMBLDC) motor. Its failure may lead to a decrease in system reliability. Hence, this article proposes a novel methodology for the Hall sensors fault diagnosis and fault-tolerant control in PMBLDC motor drives. Initially, the Hall sensor faults are analyzed and classified into three fault types. Taking the Hall signal as the system state and the conducted MOSFETs as the system event, the extended finite state machine (EFSM) of the motor in operation is established. Meanwhile, a motor speed observer based on the super twisting algorithm (STA) is designed to obtain the speed signal of the proposed strategy. On this basis, a real-time Hall sensor fault diagnosis strategy is established by combining the EFSM and the STA speed observer. Moreover, this article proposes a Hall signal reconstruction strategy, which can generate compensated Hall signal to realize fault-tolerant control under single or double Hall sensor faults. Finally, theoretical analysis and experimental results validate the superior effectiveness of the proposed real-time fault diagnosis and fault-tolerant control strategy.

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“…Using the resource remapping techniques for the pipeline registers and for the CPU working registers, the operation of context switching takes maximum three clock cycles, regardless of the number and size of the registers that need saving. In the proposed model, nHSE is a finite state machine [23] implemented as an integral part of the processor.…”

Section: Contributions Regarding the Implementation Of The Nmpra Archmentioning

confidence: 99%

Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms

Zagan

Găitan

2017

IET Computers & Digital Techniques

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Taking into consideration the requirements of real-time embedded systems, the processor scheduler must guarantee a constant scheduling frequency, providing determinism and predictability of tasks execution. The purpose of this study is to implement the nMPRA (multi pipeline register architecture) processor into field-programmable gate array, and to integrate the already existing scheduling methods, thus providing a preemptive schedulability analysis of the proposed architecture based on the pipeline assembly line and hardware scheduler. This study describes a hardware implementation of the real-time scheduler named nHSE (hardware scheduler engine for n tasks) and presents the results obtained using the appropriate schedulability methods used in real-time environments. The scheduling and task switch operations are the main source of non-determinism, being successfully dealt with real-time nMPRA concept, in order to improve the system's functionality. Some mechanisms used for synchronisation and inter-task communication are also taken into consideration.

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Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits

Cited by 9 publications

References 15 publications

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Real-Time Fault Diagnosis and Fault-Tolerant Control Strategy for Hall Sensors in Permanent Magnet Brushless DC Motor Drives

Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms

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