Magnetic Flip Flops for Space Applications

Hass, K.J.; Donohoe, G.W.; Hong, Yang‐Ki; Choi, Byoung Kyu

doi:10.1109/tmag.2006.879738

Cited by 19 publications

(9 citation statements)

References 6 publications

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“…II-2, the varistor-like symbols, labeled MTJ1 and MTJ2, represent the two MTJs needed to harden the latch. However, if the dielectric layer is damaged by an incident particle, the magneto-resistance value drops and any hardening benefit provided by the MTJs is nullified [16]. Also, like the resistors used in RC hardening, MTJs create a low pass filter that limits magnetic hardening use to low bandwidth applications.…”

Section: ) Magnetic Tunnel Junction Hardeningmentioning

confidence: 99%

Redundancy Based on a Fault-Tolerant Gate Array Cell

Tyurin¹,

Kamenskih²

2017

VVSUTR

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Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs,

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Section: ) Magnetic Tunnel Junction Hardeningmentioning

confidence: 99%

Redundancy Based on a Fault-Tolerant Gate Array Cell

Tyurin¹,

Kamenskih²

2017

VVSUTR

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“…In [47] new method of hamming code checks the multiple column data with improved speed. [30] Elaborates the usage of magnetic flip-flops. The advantage of magnetic memories is being very much resistant to radiation.…”

Section: Cmos Srammentioning

confidence: 99%

Single Event Upset Detection and Hardening schemes for CNTFET SRAM – A Review

Rajalakshmi¹,

Sudhakar²

2015

JESTR

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Carbon nanotubes (CNT) provide a better alternative of silicon, when it comes to nano scales. Thanks to its high stability and high performance of carbon nanotube, CNT based FET (CNTFET) devices which are gaining popularity of late. Single Event Upset (SEU) in a device is caused due to radiation. Radiation can be through two ways, one due to charge particles present in the atmosphere and other due to alpha particles. In this article we review some of the detection and hardening schemes in CMOS SRAM and make related simulations on CNTFET SRAM. The aim of this paper is to present the challenges the CNTFET SRAM is facing when the radiation effects are introduced. A full experimentation of all the schemes of detection and correction schemes will be beyond the scope, so only certain experiments that can be well carried out with CNTFET SRAM memory is more focussed.

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“…The first is a differential sensing latch that uses the MTJ resistance to provide SEE resistance [162][163][164][165].…”

Section: Differential Mtj Latchmentioning

confidence: 99%

“…For anything other than trivial cases, the state of the logic function must be determined by The final category of reconfigurable hardware using MTJs comprises those approaches that simply replace the configuration memory elements in the circuit with latches that use MTJs for non-volatile storage, such as those that are the subject of this research [162,164,174]. The MTJ latches require relatively high power consumption for the magnetic write operation, and the low magnetoresistance ratio implies a relatively slow read operation, so these latches are best used for configuring the interconnections and logical operations rather than acting as scratchpad memory for data processing [160].…”

Section: Mtjs Applied To Programmable Logicmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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Magnetic Flip Flops for Space Applications

Cited by 19 publications

References 6 publications

Redundancy Based on a Fault-Tolerant Gate Array Cell

Redundancy Based on a Fault-Tolerant Gate Array Cell

Single Event Upset Detection and Hardening schemes for CNTFET SRAM – A Review

Magnetic Random Access Memory for Embedded Computing

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