MAC Implementation using Vedic Multiplication Algorithm

Abstract

The paper presents the implementation of MAC (multiplieraccumulator) unit using Vedic multiplier. The speed of MAC depends on the speed of the multiplier. The Vedic multiplier uses "Urdhva Tiryagbhyam" algorithm. The proposed MAC unit is coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. The MAC is implemented on a FPGA device XC2S200-6PQ208 using Xilinx ISE10.1 tool. The proposed design shows improvement of speed over the design presented in [1]. General TermsAlgorithms.

Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier

“…They have used a carry-save adder architecture, which, as per their claim, reduces the propagation delay significantly. They have also proposed a multiplier-accumulator (MAC) unit using Vedic mathematics algorithm, the UrdhvaTiryagbhyam Sutra in [5].…”

Vedic Mathematics for Digital Signal Processing Operations: A Review

“…A MAC unit based on "Urdhva tiryakbhyam' algoriothm has been implemented on FPGA in [16]. In this the multiply accumulate unit computes product of two numbers and adds the product to accumulator.…”

“…[1]- [16] Urdhva tiryakbhyam" algoriothm is considered to be the best approach for speedy multiplication. According to ref.…”

“…[1]- [16] it can be understood that FFT is an algorithm which calculates N point DFT, FFT implementation needs large number of multiplications which are very complex and time consuming. Such issues can be solved by implementing multipliers by using Vedic mathematical operations.…”