M5 based EDGE architecture modeling

Abstract

EDGE (Explicit Data Graph Execution) architec tures, a class of architectures distinct from traditional RISe and else architectures, have advantages that align well with current technology trends such as power limitations and the need for adaptive exploitation of parallelism. To better under stand the architectural and microarchitectural design spaces of EDGE architectures, we have developed a flexible MS based simulator for EDGE architectures. mS..edge includes a general high-level timing model and ISA support of one specific EDGE ISA. The high-level timing model is not designed to target a specific implementation but common characteristics of EDGE architectures, permitting faster development of a range of microarchitectures. The MS infrastructure was used because of its high functionality and performance fidelity. The specific EDGE ISA we support is the TRIPS ISA, due to its well-specified ISA and relatively mature compiler. mS..edge can execute binaries generated by the TRIPS toolchain and provides a high-level simulation template for EDGE architectures. Our experimental results show that the difference in execution cycles of mS..edge is within 11 % on average, compared to the cycle-accurate simulator provided by the TRIPS group. Thus, mS..edge benefits from both the flexible infrastructure ofMS and acceptable model accuracy, while maintaining both reasonable simulation speed and the ability to quickly explore EDGE-based microarchitectural design spaces.

Modeling and simulation of distributed fetch front-end based on M5-edge

“…M5-edge [2] as the only one simulator which was based on widely used open source simulators for EDGE architectures developed a high-level timing model. It was based on the well-known M5 simulator [3] .…”

“…The fetch unit of idealization resulted in two main problems: (1) the research had to proceed under the condition of idealization fetch front end; (2) it was hard to study the influence of micro-architectures in fetch stage. This paper expanded the fetch unit for the M5-edge, achieved the model of distributed fetch unit and estimated the performance.…”