EDGE (Explicit Data Graph Execution) architec tures, a class of architectures distinct from traditional RISe and else architectures, have advantages that align well with current technology trends such as power limitations and the need for adaptive exploitation of parallelism. To better under stand the architectural and microarchitectural design spaces of EDGE architectures, we have developed a flexible MS based simulator for EDGE architectures. mS..edge includes a general high-level timing model and ISA support of one specific EDGE ISA. The high-level timing model is not designed to target a specific implementation but common characteristics of EDGE architectures, permitting faster development of a range of microarchitectures. The MS infrastructure was used because of its high functionality and performance fidelity. The specific EDGE ISA we support is the TRIPS ISA, due to its well-specified ISA and relatively mature compiler. mS..edge can execute binaries generated by the TRIPS toolchain and provides a high-level simulation template for EDGE architectures. Our experimental results show that the difference in execution cycles of mS..edge is within 11 % on average, compared to the cycle-accurate simulator provided by the TRIPS group. Thus, mS..edge benefits from both the flexible infrastructure ofMS and acceptable model accuracy, while maintaining both reasonable simulation speed and the ability to quickly explore EDGE-based microarchitectural design spaces.
Control flow speculation plays a pushing role to the performance of block-atomic EDGE architectures. Hyperblock predictors, which leverage the style of "Exit + Target" to predict the next hyperblock address, enable high efficient hyperblock-level control flow speculation for EDGE architectures. Recently, a series of binary prediction techniques have been studied and modified to adapt for the exit predictor in hyperblock predictors, including the O-GEHL prediction technique, which was first presented at 1st Championship Branch Prediction Competition. Our paper investigated different mispredict sources in O-GEHL based exit predictor in hyperblock predictors, and proposed two improved strategies: the O-GEHL based exit predictor without chooser and the O-GEHL based exit predictor employing binary O-GEHL prediction. Performance evaluation results showed that: the proposal without chooser outperformed previously published one by 0.7% with the hardware resource ranging from 16KB to 1MB; the proposal employing 8 binary O-GEHL predictor improved the performance by 3% with the largest hardware resource in this paper (1MB); the proposal employing 4 binary O-GEHL predictor for the first 4 exits averagely improved the performance by 2% with the hardware resource ranging from 16KB to 1MB.
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