LUT-based FPGA technology mapping under arbitrary net-delay models

Cong, Jason; Ding, Yuzheng; Gao, Tong; Chen, Kuang-Chien

doi:10.1016/0097-8493(94)90063-9

Cited by 13 publications

(4 citation statements)

References 10 publications

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“…First, general static net-delay models were used in the FlowMap-d algorithm [Cong et al , 1994. It uses binary search to determine the minimum height K-feasible cut.…”

Section: The Flowmap Familymentioning

confidence: 99%

Combinational logic synthesis for LUT based field programmable gate arrays

Cong

Ding

1996

ACM Trans. Des. Autom. Electron. Syst.

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103

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The increasing popularity of the field programmable gate-array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K-input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic techniques. A comprehensive list of references is compiled in the attached bibliography.

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“…First, general static net-delay models were used in the FlowMap-d algorithm [Cong et al , 1994. It uses binary search to determine the minimum height K-feasible cut.…”

Section: The Flowmap Familymentioning

confidence: 99%

Combinational logic synthesis for LUT based field programmable gate arrays

Cong

Ding

1996

ACM Trans. Des. Autom. Electron. Syst.

Self Cite

103

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“…Therefore, we can derive the range of to be . Based on (3), similar to the approach in [7] for homogeneous LUT mapping with the arbitrary fixed net delay model, we construct a sorted height array, denoted , 8 which includes all the distinct labels that are in the range of (3). The size of the height array is at most .…”

Section: (D)mentioning

confidence: 99%

Performance-driven technology mapping for heterogeneous FPGAs

Cong

2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In order to maximize performance and device utilization, the recent generation of field programmable gate arrays (FPGAs) take advantage of speed and density benefits resulting from heterogeneous FPGAs, which can be classified into heterogeneous FPGAs without bounded resources or heterogeneous FPGAs with bounded resources. In this paper, we study the technology mapping problem for heterogeneous FPGAs with or without bounded resources under the objective of delay optimization. We present the first polynomial-time delay optimal technology mapping algorithm, named HeteroMap, for heterogeneous FPGAs without bounded resources. Taking different delays of heterogeneous lookup tables (LUTs) into consideration, the HeteroMap algorithm computes the minimum mapping delay of a circuit based on a series of minimum-height -feasible cut computations at each node in the circuit. We then study the technology mapping problem for delay minimization for heterogeneous FPGAs with bounded resources. We show that this problem is NP-hard for general networks, in contrast to the delay minimization mapping problem for heterogeneous FPGAs without bounded resources, but can be solved optimally in pseudopolynomial time for trees. We then present two heuristic algorithms to solve this problem for general networks. We have successfully applied these algorithms on MCNC benchmarks on commercial FPGAs. Encouraging results on delay and area reduction are reported.

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“…Under such conditions, minimizing the depth of the mapped network does not accurately capture the performance of the circuit after placement and routing. More recent mapping algorithms such as Flowap-d [7], Bias-Clus [4] and Edge-Map [9] consider the delays of the wires during mapping. Flowmap-d assumes that each net may have a different delay but uses the same delay for every segment of net, while Bias-Clus and Edge-Map accommodate nonuniform delays for different segments of the same net.…”

Section: Introductionmentioning

confidence: 99%

Placement-driven technology mapping for LUT-based FPGAs

Lin¹,

Jagannathan²,

Cong³

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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In this paper, we study the problem of placement-driven technology mapping for and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.

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LUT-based FPGA technology mapping under arbitrary net-delay models

Cited by 13 publications

References 10 publications

Combinational logic synthesis for LUT based field programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

Performance-driven technology mapping for heterogeneous FPGAs

Placement-driven technology mapping for LUT-based FPGAs

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