Placement-driven technology mapping for LUT-based FPGAs

Abstract

In this paper, we study the problem of placement-driven technology mapping for and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.

Optimal simultaneous mapping and clustering for FPGA delay optimization

“…We select the cut and combination with the smallest area increase. The area cost function combines the estimation method in [11] and the iterative approach in [16].…”

“…It is an important synthesis step for FPGA design flow because it directly defines the number of LUTs used for the design and the critical path length passing through these LUTs. There are many technology mapping algorithms published in the literature to improve mapping depth/delay [7][9] [16][18] [25], area [7][11] [12][18] [19], or power consumption [3][8] [13] [14]. FlowMap [9] is the first algorithm to guarantee a depth-optimal mapping solution in polynomial time under the unit delay model.…”

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

“…8 The area optimization problem was proven to be NP-hard when mapping is applied on 4-or-moreinput LUTs, and as such heuristics were developed to properly address such optimizations. 9,10 Ideas in the same context as our proposed approach, trying to use Boolean matching techniques for the optimization of the mapping process have been presented. Some proposed a Boolean matching technique for mapping on networks of programmable logic blocks (PLBs), 11 expressing it as a Boolean satis¯ability problem; however their approach remained algorithmic since they did not speci¯cally exploit the available architecture while performing the Boolean matching.…”

The effect of post-layout pin permutation on timing

“…To take this into account, one may incorporate the PinMap algorithm into technology mapping approaches that do consider post-layout interconnect delays (e.g. [6]). We are unaware of any such study, but it would be an interesting one, and should produce improved results.…”