Performance-driven technology mapping for heterogeneous FPGAs

Abstract

Abstract-In order to maximize performance and device utilization, the recent generation of field programmable gate arrays (FPGAs) take advantage of speed and density benefits resulting from heterogeneous FPGAs, which can be classified into heterogeneous FPGAs without bounded resources or heterogeneous FPGAs with bounded resources. In this paper, we study the technology mapping problem for heterogeneous FPGAs with or without bounded resources under the objective of delay optimization. We present the first polynomial-time delay optimal technology mapping algorithm, named HeteroMap, for heterogeneous FPGAs without bounded resources. Taking different delays of heterogeneous lookup tables (LUTs) into consideration, the HeteroMap algorithm computes the minimum mapping delay of a circuit based on a series of minimum-height -feasible cut computations at each node in the circuit. We then study the technology mapping problem for delay minimization for heterogeneous FPGAs with bounded resources. We show that this problem is NP-hard for general networks, in contrast to the delay minimization mapping problem for heterogeneous FPGAs without bounded resources, but can be solved optimally in pseudopolynomial time for trees. We then present two heuristic algorithms to solve this problem for general networks. We have successfully applied these algorithms on MCNC benchmarks on commercial FPGAs. Encouraging results on delay and area reduction are reported.

Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters

“…To concretize our measurements we focus on multiplier-based hard circuits, which are now common in modern FPGAs, but the concepts should apply to many kinds of circuits, including block memory. Previous solutions to improve the usage of hard circuits include adding extra functionality to hard circuits (examples include Altera's DSP block and Xilinx's XtremeDSP [3], [2]) and novel targetting of hard circuits in CAD flow stages [4], [5], [6]. Another approach is taken in the Virtex-II where programmable routing bits are shared between hard circuits to save on programmable routing area [7].…”

Technology mapping algorithms for hybrid fpgas containing lookup tables and plas

“…To date, most research in FPGA technology mapping has focused on FPGAs containing homogeneous type of resources, although recently, technology mapping algorithms for devices with LUTs of differing input sizes [19], [20] and PLAs have been presented. In [21], a technology mapping algorithm for devices with -input, single-output macrocells was presented.…”

Using DSP blocks for ROM replacement: a novel synthesis flow

“…The problem of mapping resources in heterogeneous FPGAs is considered in [6], where a more fine grain view of heterogeneity is taken than [5], and mapping logic to a dual level hierarchy of LUT sizes is examined. A logic packing algorithm is proposed and implemented which reduces routing delays by 6% over Altera's Max+PlusII design suite and with equivalent computation time to other techniques.…”