Using DSP blocks for ROM replacement: a novel synthesis flow

Abstract

This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be applied to any FPGA architecture containing embedded multiplication, however this paper focuses on using the DSP blocks of Altera Stratix and Stratix II architectures. The transformation is combined with other resource transfers and integrated in a synthesis flow targeting designs implemented on heterogeneous FPGAs. The main advantage of such a system is in handling user constraints on each type of resource: DSP block, LUT and ROM, in addition to timing-related constraints. The flow is based on an extension to the Altera Quartus II synthesis software and Quartus University Interface Program (QUIP) framework. Results are provided for implementations of benchmark algorithms and it is shown through a design-space exploration that the set of achievable designs for the algorithms has been extended by the use of the proposed methods.

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

“…In the context of FPGA technology, [14] combines technology mapping to homogeneous fine-grain FPGAs with placement and routing, although does not consider heterogeneous fabrics. More recent FPGA related works on technology mapping consider embedded memories, for example [15] and there is also work on usage of DSP blocks [16]. In contrast to the paper we present here, existing works have not considered the heterogeneous technology mapping problem in a context where the modules have to be reused when the device is configured for a set of different applications.…”

“…Similarly, if δ uv1 is equal to one then equation (12) is trivially satisfied, as long as x v is within the device boundary. By summing these variables (16) ensures that at least one variable is zero, ensuring that any two nodes do not overlap.…”

“…Once the regions are assigned, the clock period is minimised with constraints on the regions (see Figure 1). The sum of the relaxed decision variables is then minimised to reduce the binary decision variables δ uvx (12)(13)(14)(15)(16)(17) to their minimum value, as the smallest of these variables implies the least overlap (see Section IV-B for more detail). Finally, the relaxed variable to round is determined for this iteration, thus gradually avoiding overlap between computational nodes.…”

“…(11) can be represented in a mathematical program by introducing four binary variables δ uv1 , δ uv2 , δ uv3 and δ uv4 as in (12)(13)(14)(15)(16)(17), where (16) ensures that at least one of the terms in (11) is true. A x is the constraint on the device width, and A y is the constraint on the device height, the overall area constraint A = A x A y .…”

“…The heuristic technique developed is based around a controlled relaxation of the binary decision variables δ uvx (12)(13)(14)(15)(16)(17) to reals in the range [0, 1]. Removing the integrality allows fast solution through, for example, the Simplex method [29], and is a commonly employed method in integer programming solvers.…”