Low write-current magnetic random access memory cell with anisotropy-varied free layers

Fukami, Shunsuke; Honjo, H.; Suzuki, T.; Ishiwata, N.

doi:10.1063/1.3032894

Cited by 7 publications

(4 citation statements)

References 7 publications

(2 reference statements)

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“…Among several MRAM cell structures, the 2T1MTJ cell [1] is desirable for high-speed applications because it requires no accurate current control (Table I). We have demonstrated 250-MHz [2] and 32-Mb [3] macros with 2T1MTJ cells, where writing was performed with a magnetic field [4]. For cost performance that is comparable or superior to existing memories such as eSRAM and eDRAM, reducing write-current to less than 0.2 mA is indispensable (Fig.…”

Section: T1mtj Cell Structurementioning

confidence: 99%

Current Status and Future Challenge of Embedded High-speed MRAM

Fukami¹,

Suzuki²,

Nagahara³

et al. 2010

Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials

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Section: T1mtj Cell Structurementioning

confidence: 99%

Current Status and Future Challenge of Embedded High-speed MRAM

Fukami¹,

Suzuki²,

Nagahara³

et al. 2010

Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials

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“…5 We have further proposed a shape-varying MTJ ͑SVM͒. 6 The SVM structure led to both a low write current and a high MR ratio. These properties are suitable for use in operations over 500 MHz.…”

Section: Introductionmentioning

confidence: 99%

Performance of shape-varying magnetic tunneling junction for high-speed magnetic random access memory cells

Honjo

Fukami

Nebashi

et al. 2009

Journal of Applied Physics

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We have developed a shape-varying magnetic tunneling junction ͑MTJ͒ ͑SVM͒ which has a high MR ratio and low write current for use in high-speed magnetic random access memory ͑MRAM͒ cells. Combining NiFe that has low anisotropy to CoFeB which has high anisotropy through the nonmagnetic layer by interlayer exchange coupling ͑synthetic ferromagnetic coupling free layer: SFF͒, the anisotropy of SFF was reduced much more than that of CoFeB, and the MR ratio was improved much more than that of NiFe. The switching magnetic field ͑H sw ͒ of SFF was reduced as the thickness of NiFe increased. The H sw of SFF for 0.24ϫ 0.48 m 2 MTJ was 30 Oe when the thickness of CoFeB was 1.5 nm and that of NiFe was 3.0 nm. Furthermore H sw was reduced to 18 Oe by varying the shape of the MTJ of NiFe to 0.48ϫ 0.48 m 2 ; the shape of the MTJ of CoFeB was not changed ͑0.24ϫ 0.48 m 2 ͒. Combining the SVM and a write-line-inserted structure, we obtained a write current of 0.9 mA and an MR ratio of 140%. The H sw was 40 Oe and its thermal stability factor was 82. These properties are sufficient for operating MRAMs over 500 MHz.

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“…The CT height of the eDRAM with conventional COB structure is 5 times taller than that of the pure logic, while the LIC-eDRAM structure reduces the CT height by approximately 2-fold. The LIC-eDRAM is categorized as a ''BEOL memory'', in which memory elements are located in the BEOL layers, such as embedded MRAM, [6][7][8] ReRAM, [9][10][11] and FeRAM. 12) Since the 28-nm-node CMOS logic LSI implements a porous low-k film in the Cu BEOL layers, the cylinder capacitors for the LIC-eDRAM should be embedded in the porous low-k films.…”

Section: Introductionmentioning

confidence: 99%

Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

Kume

Inoue

Hijioka

et al. 2012

Jpn. J. Appl. Phys.

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We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

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Low write-current magnetic random access memory cell with anisotropy-varied free layers

Cited by 7 publications

References 7 publications

Current Status and Future Challenge of Embedded High-speed MRAM

Current Status and Future Challenge of Embedded High-speed MRAM

Performance of shape-varying magnetic tunneling junction for high-speed magnetic random access memory cells

Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

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