Performance of shape-varying magnetic tunneling junction for high-speed magnetic random access memory cells

Honjo, H.; Fukami, Shunsuke; Nebashi, R.; Suzuki, T.; Ishiwata, N.; Sugibayashi, Toshio

doi:10.1063/1.3062825

Cited by 3 publications

(5 citation statements)

References 9 publications

(9 reference statements)

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“…MEI-2 reverses the layer order in the MTJ stack (i.e. as in [83]). In MEI-2, the free layer resides on the bottom-and the oxide tunneling layer, fixed layer, etc are placed on top as shown in figure 28(b).…”

Section: Mei-2mentioning

confidence: 99%

Nanomagnet logic: progress toward system-level integration

Niemier

Bernstein

Csaba

et al. 2011

J. Phys.: Condens. Matter

158

172

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Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

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Section: Mei-2mentioning

confidence: 99%

Nanomagnet logic: progress toward system-level integration

Niemier

Bernstein

Csaba

et al. 2011

J. Phys.: Condens. Matter

158

172

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“…[8][9][10] We previously proposed a shape-varying MTJ (SVM), 11 which switched by magnetic field, as a three-terminal cell. 12,13 This cell is not scalable, however, the switching current of under 1 mA was enough small to demonstrate logic circuit. The MR ratio of the SVM in which the CoFeB film was used as a free layer was high enough, however, it had a big switching current distribution because of the large intrinsic anisotropy of CoFeB.…”

Section: Introductionmentioning

confidence: 99%

“…The MR ratio of the SVM in which the CoFeB film was used as a free layer was high enough, however, it had a big switching current distribution because of the large intrinsic anisotropy of CoFeB. 12 Although the switching current distribution was reduced by using the NiFe free layer, the MR ratio also decreased, 12 which caused fail bits of the magnetic logic circuits.…”

Section: Introductionmentioning

confidence: 99%

Magnetic tunneling junction with Fe/NiFeB free layer for magnetic logic circuits

Honjo¹,

Fukami

Nebashi³

et al. 2012

Journal of Applied Physics

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We have developed a shape varying magnetic tunneling junction (SVM) with a Fe/NiFeB free layer for use in magnetic logic circuits. Inserting the thin Fe film between an NiFeB free layer and MgO tunneling barrier improved the magnetoresistance (MR) ratio: it increased up to 130%, as the thickness of the Fe film increased. In addition, the switching current distribution of the SVM was reduced to 8%. By using NiFeB as a free layer, the roughness under the MgO was reduced and the crystallization of the MgO was enhanced. This led to both the high MR ratio and the low switching current distribution. Our developed Fe (0.4 nm)/NiFeB free layer satisfies the requirement of the MTJ's characteristics that the magnetic logic circuits operate with a high bit yield.

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“…The 2T1MTJ cell area is proportional to the writing current for switching the magnetization of the magnetic storage layer. To reduce cell area, we have been reducing the switching current of the magnetic storage layer [6]. As another scheme for cell area reduction, we use boosted a wordline technique in the 32Mb MRAM design.…”

mentioning

confidence: 99%

“…We use read-bitline-divided and half-pitch-shift architectures to reduce the read-access time. The 2T1MTJ structure is suitable for reducing switching current [6]. The largest switching current is less than 1mA and the mean switching current is 0.6mA.…”

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confidence: 99%

A 90nm 12ns 32Mb 2T1MTJ MRAM

Nebashi

Sakimura

Honjo

et al. 2009

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1][2][3][4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of standalone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time. Figure 27.4.1 shows a block diagram of 32Mb MRAM.The interface is compatible with asynchronous high-speed SRAMs. Our developed 32Mb MRAM includes four synchronous 10Mb macros (MMACs) and peripheral circuits. Each MMAC includes ten 1Mb sub macros (SMACs). One of the peripheral circuits is an asynchronous-to-synchronous convertor and an ECC encoder/decoder using a (32 + 8) bit Reed-Solomon code, which effectively corrects multiple errors. An internal power-supply circuit supplies a 1V core voltage (V DD ) and 1.5V boosted voltage (V DH ). Each SMAC includes four sets of redundant columns and two sets of redundant rows.To achieve an increase of memory capacity, reduction of cell area is essential. The 2T1MTJ cell area is proportional to the writing current for switching the magnetization of the magnetic storage layer. To reduce cell area, we have been reducing the switching current of the magnetic storage layer [6]. As another scheme for cell area reduction, we use boosted a wordline technique in the 32Mb MRAM design. The selected wordline is driven by a voltage V DH , which is higher than V DD . A 1.5V VDH improves drivability of cell transistors, and the gate width of cell transistors is reduced by half, as shown in Fig. 27.4.2. We achieve a memory cell area of 0.66×2.08µm 2 with a 1mA conducting current. The area is comparable to that of a 6T SRAM in the same process technology.However, the use of a boosted wordline technique causes access-time degradation because boosted wordline drivers are complicated compared to normal ones. To diminish the degradation, we use a specific type of the wordline driver with an additional power supply, as shown in Fig. 27.4.3. Standalone memories are permitted to use an additional power supply because internal power-supply circuits are shared by many memory cell arrays. Since the voltage of a wordline, V DH , is higher than V DD , the wordline driver requires a level converter. In standby mode, the row precharge signal (RP) is at the low level and node one, N1, is precharged to the V DH . After addresses are determined, RP is at V DH...

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Performance of shape-varying magnetic tunneling junction for high-speed magnetic random access memory cells

Cited by 3 publications

References 9 publications

Nanomagnet logic: progress toward system-level integration

Nanomagnet logic: progress toward system-level integration

Magnetic tunneling junction with Fe/NiFeB free layer for magnetic logic circuits

A 90nm 12ns 32Mb 2T1MTJ MRAM

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